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	Merge branch 'main' into lrufixes
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						77d47e531f
					
				@ -46,12 +46,13 @@ module loggers import cvw::*; #(parameter cvw_t P,
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  // performance counter logging 
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  logic        BeginSample;
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  logic StartSample, EndSample;
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  if((PrintHPMCounters || BPRED_LOGGER) && P.ZICNTR_SUPPORTED) begin : HPMCSample
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  if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample
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    integer           HPMCindex;
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    logic             StartSampleFirst;
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    logic             StartSampleDelayed, BeginDelayed;
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    logic             EndSampleFirst;
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    logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0];
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    logic              EndSampleDelayed;
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    string  HPMCnames[] = '{"Mcycle",
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                            "------",
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@ -80,6 +81,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
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                            "Divide Cycles"
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                          };
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    always_comb
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      if (TEST == "embench") begin  
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        StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
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@ -92,14 +94,13 @@ module loggers import cvw::*; #(parameter cvw_t P,
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        EndSampleFirst = '0;
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      end
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    // this code needs to be with embench and coremark but not the else condition
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    if (TEST == "embench" | TEST == "coremark") begin
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      logic EndSampleDelayed;
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      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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    end else begin
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      assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
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    end
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    flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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    always_comb
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      if (TEST == "embench" | TEST == "coremark") begin
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        EndSample = EndSampleFirst & ~ EndSampleDelayed;
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      end else begin
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        EndSample = DCacheFlushStart & ~DCacheFlushDone;
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      end
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  /*
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    if(TEST == "embench") begin
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