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5e4f4c2072
cvw/testbench
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Rose Thompson 5e4f4c2072 Simple change to ensure Trapped instructions are included with rvvi as 
valid instructions. Required for functional coverage.
2024-11-14 16:14:02 -06:00
..
common Simple change to ensure Trapped instructions are included with rvvi as 2024-11-14 16:14:02 -06:00
coverage pmp coverage 2024-05-02 11:53:32 -07:00
sdc More name updates. 2024-08-21 10:51:24 -07:00
Makefile Fixes to memfile generation for rv32. Updated new misa.B in imperas.ic, but need new version of ImperasDV to test 2024-07-04 07:36:56 -07:00
testbench_fp.sv Restore testbench_fp to load from vectors directory 2024-09-29 00:57:41 -07:00
testbench.sv Removed unnecessary display statement from testbench for DTIM versions 2024-10-26 02:12:43 -07:00
tests_fp.vh Restore testbench_fp to load from vectors directory 2024-09-29 00:57:41 -07:00
tests.vh Added btbthrash to tests.vh. 2024-10-30 16:07:05 -05:00
wallywrapper.sv Merge branch 'main' of github.com:openhwgroup/cvw into spiboot 2024-08-06 17:09:39 -05:00