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https://github.com/openhwgroup/cvw
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Replace tabs with spaces in testbench_fp
This commit is contained in:
Jordan Carlin
parent
5618e27424
commit
4081d4de58
@ -10,15 +10,15 @@
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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@ -53,95 +53,94 @@ module testbench_fp;
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parameter MAXVECTORS = 8388610;
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// FIXME: needs cleaning of unused variables (jes)
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string Tests[]; // list of tests to be run
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logic [2:0] OpCtrl[]; // list of op controls
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logic [2:0] Unit[]; // list of units being tested
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logic WriteInt[]; // Is being written to integer resgiter
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logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
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logic [1:0] Fmt[]; // list of formats for the other units
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string Tests[]; // list of tests to be run
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logic [2:0] OpCtrl[]; // list of op controls
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logic [2:0] Unit[]; // list of units being tested
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logic WriteInt[]; // Is being written to integer resgiter
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logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
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logic [1:0] Fmt[]; // list of formats for the other units
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logic clk=0;
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logic [31:0] TestNum=0; // index for the test
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logic [31:0] OpCtrlNum=0; // index for OpCtrl
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logic [31:0] errors=0; // how many errors
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logic [31:0] VectorNum=0; // index for test vector
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logic [31:0] FrmNum=0; // index for rounding mode
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logic [P.Q_LEN*4+7:0] TestVectors[MAXVECTORS-1:0]; // list of test vectors
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logic clk=0;
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logic [31:0] TestNum=0; // index for the test
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logic [31:0] OpCtrlNum=0; // index for OpCtrl
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logic [31:0] errors=0; // how many errors
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logic [31:0] VectorNum=0; // index for test vector
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logic [31:0] FrmNum=0; // index for rounding mode
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logic [P.Q_LEN*4+7:0] TestVectors[MAXVECTORS-1:0]; // list of test vectors
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logic [1:0] FmtVal; // value of the current Fmt
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logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
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logic WriteIntVal; // value of the current WriteInt
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logic [P.Q_LEN-1:0] X, Y, Z; // inputs read from TestFloat
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logic [P.FLEN-1:0] XPostBox; // inputs read from TestFloat
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logic [P.XLEN-1:0] SrcA; // integer input
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logic [P.Q_LEN-1:0] Ans; // correct answer from TestFloat
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logic [P.Q_LEN-1:0] Res; // result from other units
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logic [4:0] AnsFlg; // correct flags read from testfloat
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logic [4:0] ResFlg, Flg; // Result flags
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logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
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logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
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logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit
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logic [P.Q_LEN-1:0] FpResExtended; // FpRes extended to same length as Ans/Res
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logic [4:0] FmaFlg, CvtFlg, DivFlg; // Outputed flags
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logic [4:0] CmpFlg; // Outputed flags
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logic AnsNaN, ResNaN, NaNGood;
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logic Xs, Ys, Zs; // sign of the inputs
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logic [P.NE-1:0] Xe, Ye, Ze; // exponent of the inputs
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logic [P.NF:0] Xm, Ym, Zm; // mantissas of the inputs
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logic XNaN, YNaN, ZNaN; // is the input NaN
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logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN
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logic XSubnorm, ZSubnorm; // is the input denormalized
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logic XInf, YInf, ZInf; // is the input infinity
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logic XZero, YZero, ZZero; // is the input zero
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logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones
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logic [P.CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
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logic IntZero;
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logic CvtResSgnE;
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logic [P.NE:0] CvtCalcExpE; // the calculated exponent
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logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
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logic [P.DIVb:0] Quot;
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logic CvtResSubnormUfE;
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logic DivStart;
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logic FDivBusyE;
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logic OldFDivBusyE;
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logic reset = 1'b0;
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logic [$clog2(P.NF+2)-1:0] XZeroCnt, YZeroCnt;
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logic [1:0] FmtVal; // value of the current Fmt
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logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
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logic WriteIntVal; // value of the current WriteInt
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logic [P.Q_LEN-1:0] X, Y, Z; // inputs read from TestFloat
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logic [P.FLEN-1:0] XPostBox; // inputs read from TestFloat
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logic [P.XLEN-1:0] SrcA; // integer input
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logic [P.Q_LEN-1:0] Ans; // correct answer from TestFloat
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logic [P.Q_LEN-1:0] Res; // result from other units
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logic [4:0] AnsFlg; // correct flags read from testfloat
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logic [4:0] ResFlg, Flg; // Result flags
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logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
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logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
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logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit
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logic [P.Q_LEN-1:0] FpResExtended; // FpRes extended to same length as Ans/Res
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logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
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logic AnsNaN, ResNaN, NaNGood;
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logic Xs, Ys, Zs; // sign of the inputs
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logic [P.NE-1:0] Xe, Ye, Ze; // exponent of the inputs
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logic [P.NF:0] Xm, Ym, Zm; // mantissas of the inputs
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logic XNaN, YNaN, ZNaN; // is the input NaN
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logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN
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logic XSubnorm, ZSubnorm; // is the input denormalized
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logic XInf, YInf, ZInf; // is the input infinity
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logic XZero, YZero, ZZero; // is the input zero
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logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones
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logic [P.CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
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logic IntZero;
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logic CvtResSgnE;
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logic [P.NE:0] CvtCalcExpE; // the calculated exponent
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logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
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logic [P.DIVb:0] Quot;
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logic CvtResSubnormUfE;
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logic DivStart;
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logic FDivBusyE;
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logic OldFDivBusyE;
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logic reset = 1'b0;
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logic [$clog2(P.NF+2)-1:0] XZeroCnt, YZeroCnt;
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// in-between FMA signals
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logic Mult;
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logic Ss;
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logic [P.NE+1:0] Pe;
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logic [P.NE+1:0] Se;
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logic ASticky;
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logic KillProd;
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logic Mult;
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logic Ss;
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logic [P.NE+1:0] Pe;
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logic [P.NE+1:0] Se;
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logic ASticky;
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logic KillProd;
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logic [$clog2(P.FMALEN+1)-1:0] SCnt;
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logic [P.FMALEN-1:0] Sm;
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logic InvA;
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logic NegSum;
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logic As;
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logic Ps;
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logic DivSticky;
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logic DivDone;
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logic DivNegSticky;
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logic [P.NE+1:0] DivCalcExp;
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logic divsqrtop;
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logic [P.FMALEN-1:0] Sm;
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logic InvA;
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logic NegSum;
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logic As;
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logic Ps;
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logic DivSticky;
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logic DivDone;
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logic DivNegSticky;
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logic [P.NE+1:0] DivCalcExp;
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logic divsqrtop;
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// Missing logic vectors fdivsqrt
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logic [2:0] Funct3E;
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logic [2:0] Funct3M;
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logic FlushE;
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logic IFDivStartE;
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logic FDivDoneE;
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logic [P.NE+1:0] UeM;
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logic [P.DIVb:0] UmM;
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logic [P.XLEN-1:0] FIntDivResultM;
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logic ResMatch; // Check if result match
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logic FlagMatch; // Check if IEEE flags match
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logic CheckNow; // Final check
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logic FMAop; // Is this a FMA operation?
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logic [2:0] Funct3E;
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logic [2:0] Funct3M;
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logic FlushE;
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logic IFDivStartE;
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logic FDivDoneE;
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logic [P.NE+1:0] UeM;
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logic [P.DIVb:0] UmM;
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logic [P.XLEN-1:0] FIntDivResultM;
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logic ResMatch; // Check if result match
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logic FlagMatch; // Check if IEEE flags match
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logic CheckNow; // Final check
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logic FMAop; // Is this a FMA operation?
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logic [P.NE-2:0] BiasE; // Bias of exponent
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logic [P.LOGFLEN-1:0] NfE; // Number of fractional bits
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logic [P.NE-2:0] BiasE; // Bias of exponent
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logic [P.LOGFLEN-1:0] NfE; // Number of fractional bits
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// FSM for testing each item per clock
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typedef enum logic [2:0] {S0, Start, S2, Done} statetype;
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@ -1040,38 +1039,38 @@ endmodule
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module readvectors import cvw::*; #(parameter cvw_t P) (
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input logic clk,
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input logic [P.Q_LEN*4+7:0] TestVector,
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input logic [P.FMTBITS-1:0] ModFmt,
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input logic [1:0] Fmt,
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input logic [2:0] Unit,
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input logic [31:0] VectorNum,
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input logic [31:0] TestNum,
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input logic [2:0] OpCtrl,
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output logic [P.Q_LEN-1:0] Ans,
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output logic [P.XLEN-1:0] SrcA,
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output logic [4:0] AnsFlg,
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output logic Xs, Ys, Zs, // sign bits of XYZ
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output logic [P.NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
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output logic [P.NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
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output logic XNaN, YNaN, ZNaN, // is XYZ a NaN
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output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
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output logic XSubnorm, ZSubnorm, // is XYZ denormalized
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output logic XZero, YZero, ZZero, // is XYZ zero
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output logic XInf, YInf, ZInf, // is XYZ infinity
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output logic XExpMax,
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output logic [P.Q_LEN-1:0] X, Y, Z,
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output logic [P.FLEN-1:0] XPostBox,
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output logic [P.NE-2:0] BiasE, // Bias of exponent
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output logic [P.LOGFLEN-1:0] NfE // Number of fractional bits
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input logic clk,
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input logic [P.Q_LEN*4+7:0] TestVector,
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input logic [P.FMTBITS-1:0] ModFmt,
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input logic [1:0] Fmt,
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input logic [2:0] Unit,
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input logic [31:0] VectorNum,
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input logic [31:0] TestNum,
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input logic [2:0] OpCtrl,
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output logic [P.Q_LEN-1:0] Ans,
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output logic [P.XLEN-1:0] SrcA,
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output logic [4:0] AnsFlg,
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output logic Xs, Ys, Zs, // sign bits of XYZ
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output logic [P.NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
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output logic [P.NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
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output logic XNaN, YNaN, ZNaN, // is XYZ a NaN
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output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
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output logic XSubnorm, ZSubnorm, // is XYZ denormalized
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output logic XZero, YZero, ZZero, // is XYZ zero
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output logic XInf, YInf, ZInf, // is XYZ infinity
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output logic XExpMax,
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output logic [P.Q_LEN-1:0] X, Y, Z,
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output logic [P.FLEN-1:0] XPostBox,
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output logic [P.NE-2:0] BiasE, // Bias of exponent
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output logic [P.LOGFLEN-1:0] NfE // Number of fractional bits
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);
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localparam Q_LEN = 32'd128;
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logic XEn;
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logic YEn;
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logic ZEn;
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logic FPUActive;
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logic XEn;
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logic YEn;
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logic ZEn;
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logic FPUActive;
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// apply test vectors on rising edge of clk
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// Format of vectors Inputs(1/2/3)_AnsFlg
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@ -1212,15 +1211,15 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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X = {TestVector[8+P.Q_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
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Ans = TestVector[8+(P.Q_LEN-1):8];
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end
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2'b01: if (P.D_SUPPORTED) begin // double
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2'b01: if (P.D_SUPPORTED) begin // double
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X = {TestVector[8+P.Q_LEN+P.D_LEN-1:8+(P.D_LEN)]};
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Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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end
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2'b00: begin // single
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2'b00: begin // single
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X = {TestVector[8+P.Q_LEN+P.S_LEN-1:8+(P.S_LEN)]};
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Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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end
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2'b10: begin // half
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2'b10: begin // half
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X = {TestVector[8+P.Q_LEN+P.H_LEN-1:8+(P.H_LEN)]};
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Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
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end
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@ -1232,15 +1231,15 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
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Ans = TestVector[8+(P.Q_LEN-1):8];
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end
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2'b01: begin // double
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2'b01: begin // double
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X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.D_LEN-1:8+(P.D_LEN)]};
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Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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end
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2'b00: begin // single
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2'b00: begin // single
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X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.S_LEN-1:8+(P.S_LEN)]};
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Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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end
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2'b10: begin // half
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2'b10: begin // half
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X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.H_LEN-1:8+(P.H_LEN)]};
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Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
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end
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@ -1252,15 +1251,15 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
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Ans = TestVector[8+(P.Q_LEN-1):8];
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end
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2'b01: if (P.D_SUPPORTED) begin // double
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2'b01: if (P.D_SUPPORTED) begin // double
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X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.D_LEN-1:8+(P.D_LEN)]};
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Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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end
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2'b00: begin // single
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2'b00: begin // single
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X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.S_LEN-1:8+(P.S_LEN)]};
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Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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end
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2'b10: begin // half
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2'b10: begin // half
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X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.H_LEN-1:8+(P.H_LEN)]};
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Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
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end
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@ -1272,15 +1271,15 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
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Ans = TestVector[8+(P.Q_LEN-1):8];
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end
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2'b01: if (P.D_SUPPORTED) begin // double
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2'b01: if (P.D_SUPPORTED) begin // double
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X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]};
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Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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end
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2'b00: if (P.F_SUPPORTED) begin // single
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2'b00: if (P.F_SUPPORTED) begin // single
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X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]};
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Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
2'b10: begin // half
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
@ -1297,18 +1296,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)];
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b10: begin // int -> quad
|
||||
2'b10: begin // int -> quad
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]};
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: begin // quad -> long
|
||||
2'b01: begin // quad -> long
|
||||
X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
|
||||
end
|
||||
2'b00: begin // quad -> int
|
||||
2'b00: begin // quad -> int
|
||||
X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
@ -1323,18 +1322,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)];
|
||||
Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // int -> double
|
||||
2'b10: begin // int -> double
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b01: begin // double -> long
|
||||
2'b01: begin // double -> long
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
|
||||
end
|
||||
2'b00: begin // double -> int
|
||||
2'b00: begin // double -> int
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.Q_LEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
@ -1349,18 +1348,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)];
|
||||
Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // int -> single
|
||||
2'b10: begin // int -> single
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b01: begin // single -> long
|
||||
2'b01: begin // single -> long
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
|
||||
end
|
||||
2'b00: begin // single -> int
|
||||
2'b00: begin // single -> int
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
@ -1375,18 +1374,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)];
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // int -> half
|
||||
2'b10: begin // int -> half
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
2'b01: begin // half -> long
|
||||
2'b01: begin // half -> long
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
|
||||
end
|
||||
2'b00: begin // half -> int
|
||||
2'b00: begin // half -> int
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user