mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 09:45:18 +00:00
Modifying tracer toward being able to run non-gc configurations in lockstep
This commit is contained in:
David Harris
parent
f1f71f6835
commit
05189d102a
@ -95,11 +95,19 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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assign FlushW = testbench.dut.core.FlushW;
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assign TrapM = testbench.dut.core.TrapM;
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assign HaltM = testbench.DCacheFlushStart;
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assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW;
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assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
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assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
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assign wfiM = testbench.dut.core.priv.priv.wfiM;
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assign InterruptM = testbench.dut.core.priv.priv.InterruptM;
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if (P.ZICSR_SUPPORTED) begin
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assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW;
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assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
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assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
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assign wfiM = testbench.dut.core.priv.priv.wfiM;
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assign InterruptM = testbench.dut.core.priv.priv.InterruptM;
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end else begin
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assign PrivilegeModeW = 2'b11;
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assign STATUS_SXL = 0;
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assign STATUS_UXL = 0;
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assign wfiM = 0;
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assign InterruptM = 0;
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end
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//For VM Verification
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assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
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@ -116,181 +124,185 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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logic valid;
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always_comb begin
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// Since we are detected the CSR change by comparing the old value we need to
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// ensure the CSR is detected when the pipeline's Writeback stage is not
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// stalled. If it is stalled we want CSRArray to hold the old value.
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if(valid) begin
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// PMPCFG CSRs (space is 0-15 3a0 - 3af)
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localparam inc = P.XLEN == 32 ? 4 : 8;
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int i, i4, i8, csrid;
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logic [P.XLEN-1:0] pmp;
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if (P.ZICSR_SUPPORTED) begin
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always_comb begin
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// Since we are detected the CSR change by comparing the old value we need to
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// ensure the CSR is detected when the pipeline's Writeback stage is not
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// stalled. If it is stalled we want CSRArray to hold the old value.
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if(valid) begin
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// PMPCFG CSRs (space is 0-15 3a0 - 3af)
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localparam inc = P.XLEN == 32 ? 4 : 8;
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int i, i4, i8, csrid;
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logic [P.XLEN-1:0] pmp;
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for (i=0; i<P.PMP_ENTRIES; i+=inc) begin
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i4 = i / 4;
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i8 = (i / inc) * inc;
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csrid = 12'h3A0 + i4;
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pmp = 0;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+0] << 0;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+1] << 8;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+2] << 16;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+3] << 24;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+4] << 32;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+5] << 40;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+6] << 48;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56;
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for (i=0; i<P.PMP_ENTRIES; i+=inc) begin
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i4 = i / 4;
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i8 = (i / inc) * inc;
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csrid = 12'h3A0 + i4;
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pmp = 0;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+0] << 0;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+1] << 8;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+2] << 16;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+3] << 24;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+4] << 32;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+5] << 40;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+6] << 48;
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pmp |= testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[i8+7] << 56;
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CSRArray[csrid] = pmp;
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end
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// PMPADDR CSRs (space is 0-63 3b0 - 3ef)
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for (i=0; i<P.PMP_ENTRIES; i++) begin
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csrid = 12'h3B0 + i;;
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pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
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CSRArray[csrid] = pmp;
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end
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// M-mode trap CSRs
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CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
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CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW;
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CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
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CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
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CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
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CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
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CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
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CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
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CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
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CSRArray[csrid] = pmp;
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end
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// S-mode trap CSRs
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CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW;
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CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222;
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CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
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CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
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CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
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CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
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CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
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CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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// PMPADDR CSRs (space is 0-63 3b0 - 3ef)
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for (i=0; i<P.PMP_ENTRIES; i++) begin
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csrid = 12'h3B0 + i;;
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pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
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CSRArray[csrid] = pmp;
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end
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// Virtual Memory CSRs
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CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
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// M-mode trap CSRs
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CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
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CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW;
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CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
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CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
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CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
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CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
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CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
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CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
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CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
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// S-mode trap CSRs
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CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW;
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CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222;
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CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
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CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
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CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
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CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
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CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
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CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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// Floating-Point CSRs
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CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
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CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
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CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
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// Virtual Memory CSRs
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CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
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// Counters / Performance Monitoring CSRs
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CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
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CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
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CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
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// mhpmevent3-31 not connected (232-33F)
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CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; // MCYCLE
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CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; // MINSTRET
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// mhpmcounter3-31 not connected (B03-B1F)
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// cycle, time, instret not connected (C00-C02)
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// hpmcounter3-31 not connected (C03-C1F)
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// Floating-Point CSRs
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CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
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CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
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CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
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// Machine Information Registers and Configuration CSRs
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CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
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CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
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CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
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CSRArray[12'h747] = 0; // mseccfg
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CSRArray[12'hF11] = 0; //mvendorid
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CSRArray[12'hF12] = 0; // marchid
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CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; // mimpid
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CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
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CSRArray[12'hF15] = 0; //mconfigptr
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// Counters / Performance Monitoring CSRs
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CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
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CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
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CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
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// mhpmevent3-31 not connected (232-33F)
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CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; // MCYCLE
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CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; // MINSTRET
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// mhpmcounter3-31 not connected (B03-B1F)
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// cycle, time, instret not connected (C00-C02)
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// hpmcounter3-31 not connected (C03-C1F)
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// Sstc CSRs
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CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0];
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// Zkr CSRs
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// seed not connected (015)
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// Machine Information Registers and Configuration CSRs
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CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
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CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
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CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
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CSRArray[12'h747] = 0; // mseccfg
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CSRArray[12'hF11] = 0; //mvendorid
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CSRArray[12'hF12] = 0; // marchid
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CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; // mimpid
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CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
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CSRArray[12'hF15] = 0; //mconfigptr
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// extra CSRs for RV32
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if (P.XLEN == 32) begin
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CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW;
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CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW;
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CSRArray[12'h757] = 0; // mseccfgh
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CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
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end
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end else begin // hold the old value if the pipeline is stalled.
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// PMP CFG 3A0 to 3AF
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int csrid;
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for(csrid='h3A0; csrid<='h3AF; csrid++)
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CSRArray[csrid] = CSRArrayOld[csrid];
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// PMP ADDR 3B0 to 3EF
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for(csrid='h3B0; csrid<='h3EF; csrid++)
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CSRArray[csrid] = CSRArrayOld[csrid];
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// Sstc CSRs
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CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0];
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// Zkr CSRs
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// seed not connected (015)
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// M-mode trap CSRs
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CSRArray[12'h300] = CSRArrayOld[12'h300];
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CSRArray[12'h302] = CSRArrayOld[12'h302];
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CSRArray[12'h303] = CSRArrayOld[12'h303];
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CSRArray[12'h304] = CSRArrayOld[12'h304];
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CSRArray[12'h305] = CSRArrayOld[12'h305];
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CSRArray[12'h340] = CSRArrayOld[12'h340];
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CSRArray[12'h341] = CSRArrayOld[12'h341];
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CSRArray[12'h342] = CSRArrayOld[12'h342];
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CSRArray[12'h343] = CSRArrayOld[12'h343];
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CSRArray[12'h344] = CSRArrayOld[12'h344];
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// extra CSRs for RV32
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if (P.XLEN == 32) begin
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CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW;
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CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW;
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CSRArray[12'h757] = 0; // mseccfgh
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CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32];
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end
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end else begin // hold the old value if the pipeline is stalled.
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// PMP CFG 3A0 to 3AF
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int csrid;
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for(csrid='h3A0; csrid<='h3AF; csrid++)
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CSRArray[csrid] = CSRArrayOld[csrid];
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// PMP ADDR 3B0 to 3EF
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for(csrid='h3B0; csrid<='h3EF; csrid++)
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CSRArray[csrid] = CSRArrayOld[csrid];
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// S-mode trap CSRs
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CSRArray[12'h100] = CSRArrayOld[12'h100];
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CSRArray[12'h104] = CSRArrayOld[12'h104];
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CSRArray[12'h105] = CSRArrayOld[12'h105];
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CSRArray[12'h140] = CSRArrayOld[12'h140];
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CSRArray[12'h141] = CSRArrayOld[12'h141];
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CSRArray[12'h142] = CSRArrayOld[12'h142];
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CSRArray[12'h143] = CSRArrayOld[12'h143];
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CSRArray[12'h144] = CSRArrayOld[12'h144];
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// M-mode trap CSRs
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CSRArray[12'h300] = CSRArrayOld[12'h300];
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CSRArray[12'h302] = CSRArrayOld[12'h302];
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CSRArray[12'h303] = CSRArrayOld[12'h303];
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CSRArray[12'h304] = CSRArrayOld[12'h304];
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CSRArray[12'h305] = CSRArrayOld[12'h305];
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CSRArray[12'h340] = CSRArrayOld[12'h340];
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CSRArray[12'h341] = CSRArrayOld[12'h341];
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CSRArray[12'h342] = CSRArrayOld[12'h342];
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||||
CSRArray[12'h343] = CSRArrayOld[12'h343];
|
||||
CSRArray[12'h344] = CSRArrayOld[12'h344];
|
||||
// Virtual Memory CSRs
|
||||
CSRArray[12'h180] = CSRArrayOld[12'h180] ;
|
||||
|
||||
// S-mode trap CSRs
|
||||
CSRArray[12'h100] = CSRArrayOld[12'h100];
|
||||
CSRArray[12'h104] = CSRArrayOld[12'h104];
|
||||
CSRArray[12'h105] = CSRArrayOld[12'h105];
|
||||
CSRArray[12'h140] = CSRArrayOld[12'h140];
|
||||
CSRArray[12'h141] = CSRArrayOld[12'h141];
|
||||
CSRArray[12'h142] = CSRArrayOld[12'h142];
|
||||
CSRArray[12'h143] = CSRArrayOld[12'h143];
|
||||
CSRArray[12'h144] = CSRArrayOld[12'h144];
|
||||
// Floating-Point CSRs
|
||||
CSRArray[12'h001] = CSRArrayOld[12'h001];
|
||||
CSRArray[12'h002] = CSRArrayOld[12'h002];
|
||||
CSRArray[12'h003] = CSRArrayOld[12'h003];
|
||||
|
||||
// Virtual Memory CSRs
|
||||
CSRArray[12'h180] = CSRArrayOld[12'h180] ;
|
||||
// Counters / Performance Monitoring CSRs
|
||||
CSRArray[12'h306] = CSRArrayOld[12'h306];
|
||||
CSRArray[12'h106] = CSRArrayOld[12'h106];
|
||||
CSRArray[12'h320] = CSRArrayOld[12'h320];
|
||||
// mhpmevent3-31 not connected (232-33F)
|
||||
CSRArray[12'hB00] = CSRArrayOld[12'hB00];
|
||||
CSRArray[12'hB02] = CSRArrayOld[12'hB02];
|
||||
// mhpmcounter3-31 not connected (B03-B1F)
|
||||
// cycle, time, instret not connected (C00-C02)
|
||||
// hpmcounter3-31 not connected (C03-C1F)
|
||||
|
||||
// Floating-Point CSRs
|
||||
CSRArray[12'h001] = CSRArrayOld[12'h001];
|
||||
CSRArray[12'h002] = CSRArrayOld[12'h002];
|
||||
CSRArray[12'h003] = CSRArrayOld[12'h003];
|
||||
// Machine Information Registers and Configuration CSRs
|
||||
CSRArray[12'h301] = CSRArrayOld[12'h301];
|
||||
CSRArray[12'h30A] = CSRArrayOld[12'h30A];
|
||||
CSRArray[12'h10A] = CSRArrayOld[12'h10A];
|
||||
CSRArray[12'h747] = CSRArrayOld[12'h747];
|
||||
CSRArray[12'hF11] = CSRArrayOld[12'hF11];
|
||||
CSRArray[12'hF12] = CSRArrayOld[12'hF12];
|
||||
CSRArray[12'hF13] = CSRArrayOld[12'hF13];
|
||||
CSRArray[12'hF14] = CSRArrayOld[12'hF14];
|
||||
CSRArray[12'hF15] = CSRArrayOld[12'hF15];
|
||||
|
||||
// Counters / Performance Monitoring CSRs
|
||||
CSRArray[12'h306] = CSRArrayOld[12'h306];
|
||||
CSRArray[12'h106] = CSRArrayOld[12'h106];
|
||||
CSRArray[12'h320] = CSRArrayOld[12'h320];
|
||||
// mhpmevent3-31 not connected (232-33F)
|
||||
CSRArray[12'hB00] = CSRArrayOld[12'hB00];
|
||||
CSRArray[12'hB02] = CSRArrayOld[12'hB02];
|
||||
// mhpmcounter3-31 not connected (B03-B1F)
|
||||
// cycle, time, instret not connected (C00-C02)
|
||||
// hpmcounter3-31 not connected (C03-C1F)
|
||||
// Sstc CSRs
|
||||
CSRArray[12'h14D] = CSRArrayOld[12'h14D];
|
||||
|
||||
// Zkr CSRs
|
||||
// seed not connected (015)
|
||||
|
||||
// Machine Information Registers and Configuration CSRs
|
||||
CSRArray[12'h301] = CSRArrayOld[12'h301];
|
||||
CSRArray[12'h30A] = CSRArrayOld[12'h30A];
|
||||
CSRArray[12'h10A] = CSRArrayOld[12'h10A];
|
||||
CSRArray[12'h747] = CSRArrayOld[12'h747];
|
||||
CSRArray[12'hF11] = CSRArrayOld[12'hF11];
|
||||
CSRArray[12'hF12] = CSRArrayOld[12'hF12];
|
||||
CSRArray[12'hF13] = CSRArrayOld[12'hF13];
|
||||
CSRArray[12'hF14] = CSRArrayOld[12'hF14];
|
||||
CSRArray[12'hF15] = CSRArrayOld[12'hF15];
|
||||
|
||||
// Sstc CSRs
|
||||
CSRArray[12'h14D] = CSRArrayOld[12'h14D];
|
||||
|
||||
// Zkr CSRs
|
||||
// seed not connected (015)
|
||||
|
||||
// extra CSRs for RV32
|
||||
if (P.XLEN == 32) begin
|
||||
CSRArray[12'h310] = CSRArrayOld[12'h310];
|
||||
CSRArray[12'h31A] = CSRArrayOld[12'h31A];
|
||||
CSRArray[12'h757] = CSRArrayOld[12'h757];
|
||||
CSRArray[12'h15D] = CSRArrayOld[12'h15D];
|
||||
end
|
||||
end
|
||||
// extra CSRs for RV32
|
||||
if (P.XLEN == 32) begin
|
||||
CSRArray[12'h310] = CSRArrayOld[12'h310];
|
||||
CSRArray[12'h31A] = CSRArrayOld[12'h31A];
|
||||
CSRArray[12'h757] = CSRArrayOld[12'h757];
|
||||
CSRArray[12'h15D] = CSRArrayOld[12'h15D];
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
// no CSRArray
|
||||
end
|
||||
|
||||
genvar index;
|
||||
@ -307,11 +319,18 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
||||
rf_wb[rf_a3] <= 1'b1;
|
||||
end
|
||||
|
||||
for(index = 0; index < NUMREGS; index += 1)
|
||||
assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
|
||||
if (P.F_SUPPORTED) begin
|
||||
assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4;
|
||||
assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
|
||||
for(index = 0; index < NUMREGS; index += 1)
|
||||
assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
|
||||
end else begin
|
||||
assign frf_a4 = '0;
|
||||
assign frf_we4 = 0;
|
||||
for(index = 0; index < NUMREGS; index += 1)
|
||||
assign frf[index] = '0;
|
||||
end
|
||||
|
||||
assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4;
|
||||
assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
|
||||
|
||||
always_comb begin
|
||||
frf_wb <= 0;
|
||||
|
||||
@ -866,12 +866,14 @@ end
|
||||
|
||||
end
|
||||
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7]));
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[11]) void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11]));
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[9]) void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9]));
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[3]) void'(rvvi.net_push("MSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[3]));
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[1]) void'(rvvi.net_push("SSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[1]));
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[5]) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[5]));
|
||||
if (P.ZICSR_SUPPORTED) begin
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7]));
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[11]) void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11]));
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[9]) void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9]));
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[3]) void'(rvvi.net_push("MSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[3]));
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[1]) void'(rvvi.net_push("SSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[1]));
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[5]) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[5]));
|
||||
end
|
||||
|
||||
final begin
|
||||
void'(rvviRefShutdown());
|
||||
|
||||
Loading…
Reference in New Issue
Block a user