Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-22 20:44:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

More name updates.

Browse Source
This commit is contained in:
Rose Thompson 2024-08-15 13:25:50 -07:00 committed by Rose
parent f603d21826
commit 113d71f1a0
3 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fpga/comport.setup
View File

@ -1,3 +1,3 @@
sudo chown ross:ross /dev/ttyUSB1
sudo chown rose:rose /dev/ttyUSB1
stty -F /dev/ttyUSB1 57600 cs8 -cstopb -parenb
cat /dev/ttyUSB1

4
testbench/common/loggers.sv
View File

@ -246,8 +246,8 @@ module loggers import cvw::*; #(parameter cvw_t P,
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
initial begin
LogFile = "branch.log"; // will break some of Ross's research analysis scripts
CFILogFile = "cfi.log"; // will break some of Ross's research analysis scripts
LogFile = "branch.log"; // will break some of Rose's research analysis scripts
CFILogFile = "cfi.log"; // will break some of Rose's research analysis scripts
//LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
file = $fopen(LogFile, "w");
CFIfile = $fopen(CFILogFile, "w");

2
testbench/sdc/sdModel.sv
View File

@ -917,7 +917,7 @@ module sdModel
WRITE_DATA: begin
oeDat<=1;
outdly_cnt<=outdly_cnt+1;
datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Ross)
datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Rose)
if ( outdly_cnt > `DLY_TO_OUTP) begin // if (outdly_cnt > 47) NAC cycles elapsed