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Add misaligned cjal and cjalr tests

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Jordan Carlin 2024-09-29 22:33:11 -07:00
parent 9711cc7348
commit 23f037e76e
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2 changed files with 4 additions and 7 deletions
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1
testbench/testbench.sv
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@ -223,7 +223,6 @@ module testbench;
"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
"arch32c_misalign": if (P.C_SUPPORTED) tests = arch32c_misalign;
endcase
end
if (tests.size() == 0 & ElfFile == "none") begin

10
testbench/tests.vh
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@ -397,7 +397,9 @@ string arch64c[] = '{
"rv64i_m/C/src/csubw-01.S",
"rv64i_m/C/src/csw-01.S",
"rv64i_m/C/src/cswsp-01.S",
"rv64i_m/C/src/cxor-01.S"
"rv64i_m/C/src/cxor-01.S",
"rv64i_m/C/src/misalign1-cjalr-01.S",
"rv64i_m/C/src/misalign1-cjr-01.S"
};
string arch64cpriv[] = '{
@ -3220,11 +3222,7 @@ string arch32c[] = '{
"rv32i_m/C/src/csub-01.S",
"rv32i_m/C/src/csw-01.S",
"rv32i_m/C/src/cswsp-01.S",
"rv32i_m/C/src/cxor-01.S"
};
string arch32c_misalign[] = '{
`RISCVARCHTEST,
"rv32i_m/C/src/cxor-01.S",
"rv32i_m/C/src/misalign1-cjalr-01.S",
"rv32i_m/C/src/misalign1-cjr-01.S"
};