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https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
Progress on fixing the cache simulator to support cbo instructions.
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@ -84,6 +84,14 @@ class Cache:
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for way in self.ways:
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for line in way:
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line.dirty = False
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# invalidate this specific line
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def cboinvalidate(self, addr):
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tag, setnum, _ = self.splitaddr(addr)
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for waynum in range(self.numways):
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line = self.ways[waynum][setnum]
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if line.tag == tag and line.valid:
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line.dirty = 0
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# invalidates the cache by setting all valid bits to False
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def invalidate(self):
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@ -108,14 +116,15 @@ class Cache:
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# performs a cache access with the given address.
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# returns a character representing the outcome:
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# H/M/E/D - hit, miss, eviction, or eviction with writeback
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def cacheaccess(self, addr, write=False):
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def cacheaccess(self, addr, write=False, clean=False):
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tag, setnum, _ = self.splitaddr(addr)
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# check our ways to see if we have a hit
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#print(f"addr is {addr:x} Set is {setnum}")
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for waynum in range(self.numways):
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line = self.ways[waynum][setnum]
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if line.tag == tag and line.valid:
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line.dirty = line.dirty or write
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line.dirty = 0 if clean else line.dirty or write
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self.update_pLRU(waynum, setnum)
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return 'H'
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@ -132,6 +141,7 @@ class Cache:
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# we need to evict. Select a victim and overwrite.
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victim = self.getvictimway(setnum)
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#print(f"addr is {addr:x} Victim is {victim} Set is {setnum}")
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line = self.ways[victim][setnum]
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prevdirty = line.dirty
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line.tag = tag
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@ -243,10 +253,15 @@ def main():
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cache.invalidate()
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if args.verbose:
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print("I")
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elif lninfo[1] == 'C' or lninfo[1] == 'L':
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cache.cboinvalidate()
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if args.verbose:
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print("C");
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else:
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addr = int(lninfo[0], 16)
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iswrite = lninfo[1] == 'W' or lninfo[1] == 'A'
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result = cache.cacheaccess(addr, iswrite)
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iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' or lninfo[1] == 'Z'
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iscboclean = lninfo[1] == 'C'
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result = cache.cacheaccess(addr, iswrite, iscboclean)
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if args.verbose:
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tag, setnum, offset = cache.splitaddr(addr)
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@ -210,6 +210,10 @@ module loggers import cvw::*; #(parameter cvw_t P,
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dut.core.lsu.LSUAtomicM[1] ? "A" :
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dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" :
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dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
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dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" : // cmo.zero
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dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" : // cmo.inval should just clear the valid and dirty bits
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dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" : // cmo.clean should act like a read in terms of the lru, but clears the dirty bit
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dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cmo.flush should just clear and the valid and drity bits
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"NULL";
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end
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