mirror of
https://github.com/openhwgroup/cvw
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Remove old imperas tests
This commit is contained in:
Jordan Carlin
parent
2f09369921
commit
ef442808a9
@ -2,26 +2,26 @@
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// testbench.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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// Modified:
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//
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// Purpose: Wally Testbench and helper modules
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// Applies test programs from the riscv-arch-test and Imperas suites
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//
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// Applies test programs from the riscv-arch-test and other custom tests
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//
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// A component of the Wally configurable RISC-V project.
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//
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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@ -50,7 +50,7 @@ module testbench;
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parameter I_CACHE_ADDR_LOGGER=0;
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parameter D_CACHE_ADDR_LOGGER=0;
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parameter RVVI_SYNTH_SUPPORTED=0;
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`ifdef USE_IMPERAS_DV
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import idvPkg::*;
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import rvviApiPkg::*;
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@ -64,7 +64,7 @@ module testbench;
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`elsif VCS
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import "DPI-C" function string getenv(input string env_name);
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string RISCV_DIR = getenv("RISCV");
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string WALLY_DIR = getenv("WALLY");
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string WALLY_DIR = getenv("WALLY");
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`else
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string RISCV_DIR = "$RISCV";
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string WALLY_DIR = "$WALLY";
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@ -82,7 +82,7 @@ module testbench;
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// DUT signals
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logic [P.AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic HREADYEXT, HRESPEXT;
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logic [P.PA_BITS-1:0] HADDR;
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logic [P.AHBW-1:0] HWDATA;
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logic [P.XLEN/8-1:0] HWSTRB;
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@ -102,12 +102,12 @@ module testbench;
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logic SDCCmd;
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logic SDCIn;
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logic [3:0] SDCCS;
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logic SDCCLK;
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logic SDCCLK;
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logic HREADY;
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logic HSELEXT;
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string ProgramAddrMapFile, ProgramLabelMapFile;
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integer ProgramAddrLabelArray [string];
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@ -118,7 +118,7 @@ module testbench;
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string tests[];
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logic DCacheFlushDone, DCacheFlushStart;
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logic riscofTest;
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logic riscofTest;
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logic Validate;
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logic SelectTest;
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logic TestComplete;
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@ -134,36 +134,30 @@ module testbench;
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if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
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INSTR_LIMIT = 0;
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//$display("TEST = %s ElfFile = %s", TEST, ElfFile);
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// pick tests based on modes supported
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//tests = '{};
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if (P.XLEN == 64) begin // RV64
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case (TEST)
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"arch64i": tests = arch64i;
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"arch64priv": tests = arch64priv;
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"arch64c": if (P.C_SUPPORTED)
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"arch64c": if (P.ZCA_SUPPORTED)
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if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
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else tests = {arch64c};
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"arch64m": if (P.M_SUPPORTED) tests = arch64m;
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"arch64a_amo": if (P.ZAAMO_SUPPORTED) tests = arch64a_amo;
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"arch64f": if (P.F_SUPPORTED) tests = arch64f;
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"arch64d": if (P.D_SUPPORTED) tests = arch64d;
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"arch64d": if (P.D_SUPPORTED) tests = arch64d;
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"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
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"arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma;
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"arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma;
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"arch64f_divsqrt": if (P.F_SUPPORTED) tests = arch64f_divsqrt;
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"arch64d_divsqrt": if (P.D_SUPPORTED) tests = arch64d_divsqrt;
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"arch64d_divsqrt": if (P.D_SUPPORTED) tests = arch64d_divsqrt;
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"arch64zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei;
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"arch64zicond": if (P.ZICOND_SUPPORTED) tests = arch64zicond;
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"imperas64i": tests = imperas64i;
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"imperas64f": if (P.F_SUPPORTED) tests = imperas64f;
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"imperas64d": if (P.D_SUPPORTED) tests = imperas64d;
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"imperas64m": if (P.M_SUPPORTED) tests = imperas64m;
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"wally64q": if (P.Q_SUPPORTED) tests = wally64q;
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"wally64a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally64a_lrsc;
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"imperas64c": if (P.C_SUPPORTED) tests = imperas64c;
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else tests = imperas64iNOc;
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"custom": tests = custom;
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"wally64i": tests = wally64i;
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"wally64i": tests = wally64i;
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"wally64priv": tests = wally64priv;
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"wally64periph": tests = wally64periph;
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"coremark": tests = coremark;
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@ -177,7 +171,7 @@ module testbench;
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"arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz;
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"arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb;
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"arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh;
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"arch64zfh_fma": if (P.ZFH_SUPPORTED) tests = arch64zfh_fma;
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"arch64zfh_fma": if (P.ZFH_SUPPORTED) tests = arch64zfh_fma;
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"arch64zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch64zfh_divsqrt;
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"arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf;
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"arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad;
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@ -188,32 +182,27 @@ module testbench;
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"arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd;
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"arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne;
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"arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh;
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endcase
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endcase
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end else begin // RV32
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case (TEST)
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"arch32e": tests = arch32e;
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"arch32e": tests = arch32e;
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"arch32i": tests = arch32i;
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"arch32priv": tests = arch32priv;
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"arch32c": if (P.C_SUPPORTED)
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"arch32c": if (P.C_SUPPORTED)
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if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
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else tests = {arch32c};
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"arch32m": if (P.M_SUPPORTED) tests = arch32m;
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"arch32a_amo": if (P.ZAAMO_SUPPORTED) tests = arch32a_amo;
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"arch32a_amo": if (P.ZAAMO_SUPPORTED) tests = arch32a_amo;
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"arch32f": if (P.F_SUPPORTED) tests = arch32f;
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"arch32d": if (P.D_SUPPORTED) tests = arch32d;
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"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
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"arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma;
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"arch32f_divsqrt": if (P.F_SUPPORTED) tests = arch32f_divsqrt;
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"arch32d_divsqrt": if (P.D_SUPPORTED) tests = arch32d_divsqrt;
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"arch32d_divsqrt": if (P.D_SUPPORTED) tests = arch32d_divsqrt;
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"arch32zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei;
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"arch32zicond": if (P.ZICOND_SUPPORTED) tests = arch32zicond;
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"imperas32i": tests = imperas32i;
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"imperas32f": if (P.F_SUPPORTED) tests = imperas32f;
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"imperas32m": if (P.M_SUPPORTED) tests = imperas32m;
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"wally32a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally32a_lrsc;
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"imperas32c": if (P.C_SUPPORTED) tests = imperas32c;
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else tests = imperas32iNOc;
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"wally32i": tests = wally32i;
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"wally32a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally32a_lrsc;
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"wally32i": tests = wally32i;
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"wally32priv": tests = wally32priv;
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"wally32periph": tests = wally32periph;
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"ahb32" : tests = ahb32;
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@ -226,7 +215,7 @@ module testbench;
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"arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz;
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"arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb;
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"arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh;
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"arch32zfh_fma": if (P.ZFH_SUPPORTED) tests = arch32zfh_fma;
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"arch32zfh_fma": if (P.ZFH_SUPPORTED) tests = arch32zfh_fma;
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"arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt;
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"arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf;
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"arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad;
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@ -236,6 +225,7 @@ module testbench;
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"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
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"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
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"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
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"arch32c_misalign": if (P.C_SUPPORTED) tests = arch32c_misalign;
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endcase
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end
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if (tests.size() == 0 & ElfFile == "none") begin
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@ -292,13 +282,13 @@ module testbench;
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always_ff @(posedge clk)
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if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET;
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else CurrState <= NextState;
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else CurrState <= NextState;
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// fsm next state logic
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always_comb begin
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// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests
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// and tests[0] == "2" refers to WallyRiscvArchTests
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riscofTest = tests[0] == "1" | tests[0] == "2";
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// riscof tests have a different signature, tests[0] == "0" refers to RiscvArchTests
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// and tests[0] == "1" refers to WallyRiscvArchTests
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riscofTest = tests[0] == "0" | tests[0] == "1";
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pathname = tvpaths[tests[0].atoi()];
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case(CurrState)
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@ -321,11 +311,11 @@ module testbench;
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default: NextState = STATE_TESTBENCH_RESET;
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endcase
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end // always_comb
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// fsm output control logic
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assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST |
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CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 |
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// fsm output control logic
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assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST |
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CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 |
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CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST;
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// this initialization is very expensive, only do it for coremark.
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// this initialization is very expensive, only do it for coremark.
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assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark";
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assign LoadMem = CurrState == STATE_LOAD_MEMORIES;
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assign ResetCntRst = CurrState == STATE_INIT_TEST;
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@ -356,7 +346,7 @@ module testbench;
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assign EcallFaultM = dut.core.priv.priv.EcallFaultM;
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else
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assign EcallFaultM = 0;
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always @(posedge clk) begin
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////////////////////////////////////////////////////////////////////////////////
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// Verify the test ran correctly by checking the memory against a known signature.
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@ -368,12 +358,12 @@ module testbench;
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$stop;
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end
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if(SelectTest) begin
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if (riscofTest) begin
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if (riscofTest) begin
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memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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elffilename = {pathname, tests[test], "ref/ref.elf"};
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ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
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end else if(TEST == "buildroot") begin
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end else if(TEST == "buildroot") begin
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memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
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elffilename = "buildroot";
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bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
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@ -397,8 +387,8 @@ module testbench;
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ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
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end
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// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
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// the addr of each label and fill the array. To expand, add more elements to this array
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// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
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// the addr of each label and fill the array. To expand, add more elements to this array
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// and initialize them to zero (also initilaize them to zero at the start of the next test)
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updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, memfilename, WALLY_DIR, ProgramAddrLabelArray);
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end
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@ -408,9 +398,9 @@ module testbench;
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$fclose(uartoutfile);
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if (TEST == "embench") begin
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// Writes contents of begin_signature to .sim.output file
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// this contains instret and cycles for start and end of test run, used by embench
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// python speed script to calculate embench speed score.
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// also, begin_signature contains the results of the self checking mechanism,
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// this contains instret and cycles for start and end of test run, used by embench
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// python speed script to calculate embench speed score.
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// also, begin_signature contains the results of the self checking mechanism,
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// which will be read by the python script for error checking
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$display("Embench Benchmark: %s is done.", tests[test]);
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if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
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@ -433,17 +423,17 @@ module testbench;
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`else
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$finish;
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`endif
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end else begin
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end else begin
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// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
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// clear signature to prevent contamination from previous tests
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if (!begin_signature_addr)
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$display("begin_signature addr not found in %s", ProgramLabelMapFile);
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else if (TEST != "embench") begin
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else if (TEST != "embench") begin
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CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
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if(errors > 0) totalerrors = totalerrors + 1;
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end
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end
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test = test + 1;
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test = test + 1;
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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@ -473,7 +463,7 @@ module testbench;
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if (LoadMem) begin
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string romfilename, sdcfilename;
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romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
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sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
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sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
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//$readmemh(romfilename, dut.uncoregen.uncore.bootrom.bootrom.memory.ROM);
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//$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
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// shorten sdc timers for simulation
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@ -548,7 +538,7 @@ module testbench;
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end
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end
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end
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end
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end
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if (P.DTIM_SUPPORTED) begin
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always @(posedge clk) begin
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if (LoadMem) begin
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@ -569,9 +559,9 @@ module testbench;
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integer adrindex;
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if (P.UNCORE_RAM_SUPPORTED)
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always @(posedge clk)
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always @(posedge clk)
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if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory)
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for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
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for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
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dut.uncoregen.uncore.ram.ram.memory.ram.RAM[adrindex] = '0;
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////////////////////////////////////////////////////////////////////////////////
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@ -584,10 +574,10 @@ module testbench;
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assign SPIIn = 1'b0;
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if(P.EXT_MEM_SUPPORTED) begin
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ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
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ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
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ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
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ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
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.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
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end else begin
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end else begin
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assign HREADYEXT = 1'b1;
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assign {HRESPEXT, HRDATAEXT} = '0;
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end
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@ -597,7 +587,7 @@ module testbench;
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/* -----\/----- EXCLUDED -----\/-----
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sdModel sdcard
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(.sdClk(SDCCLK),
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.cmd(SDCCmd),
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.cmd(SDCCmd),
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.dat(SDCDat));
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assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
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@ -607,14 +597,14 @@ module testbench;
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-----/\----- EXCLUDED -----/\----- */
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end else begin
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assign SDCIn = 1'b1;
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||||
|
||||
end
|
||||
|
||||
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .ExternalStall(RVVIStall),
|
||||
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .ExternalStall(RVVIStall),
|
||||
.HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK);
|
||||
.UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK);
|
||||
|
||||
// generate clock to sequence tests
|
||||
always begin
|
||||
@ -629,17 +619,17 @@ module testbench;
|
||||
logic [3:0] mii_txd;
|
||||
logic mii_tx_en, mii_tx_er;
|
||||
|
||||
rvvitbwrapper #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY)
|
||||
rvvitbwrapper #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY)
|
||||
rvvitbwrapper(.clk, .reset, .RVVIStall, .mii_tx_clk(clk), .mii_txd, .mii_tx_en, .mii_tx_er,
|
||||
.mii_rx_clk(clk), .mii_rxd('0), .mii_rx_dv('0), .mii_rx_er('0));
|
||||
end else begin
|
||||
assign RVVIStall = '0;
|
||||
end
|
||||
|
||||
|
||||
|
||||
/*
|
||||
// Print key info each cycle for debugging
|
||||
always @(posedge clk) begin
|
||||
always @(posedge clk) begin
|
||||
#2;
|
||||
$display("PCM: %x InstrM: %x (%5s) WriteDataM: %x IEUResultM: %x",
|
||||
dut.core.PCM, dut.core.InstrM, InstrMName, dut.core.WriteDataM, dut.core.ieu.dp.IEUResultM);
|
||||
@ -667,7 +657,7 @@ module testbench;
|
||||
|
||||
// watch for problems such as lockup, reading unitialized memory, bad configs
|
||||
watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset, .TEST); // check if PCW is stuck
|
||||
ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM,
|
||||
ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM,
|
||||
dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName);
|
||||
riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration
|
||||
loggers #(P, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
|
||||
@ -692,7 +682,7 @@ module testbench;
|
||||
end
|
||||
|
||||
// Termination condition
|
||||
// Terminate on
|
||||
// Terminate on
|
||||
// 1. jump to self loop (0x0000006f)
|
||||
// 2. a store word writes to the address "tohost"
|
||||
// 3. or PC is stuck at 0
|
||||
@ -706,13 +696,13 @@ module testbench;
|
||||
// (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero));
|
||||
// if (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)
|
||||
// $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row. Usually due to fault with no fault handler.");
|
||||
end
|
||||
end
|
||||
|
||||
DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone));
|
||||
|
||||
if(P.ZICSR_SUPPORTED) begin
|
||||
logic [P.XLEN-1:0] Minstret;
|
||||
assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
|
||||
assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
|
||||
always @(negedge clk) begin
|
||||
if (INSTR_LIMIT > 0) begin
|
||||
if((Minstret != 0) & (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
|
||||
@ -758,14 +748,14 @@ end
|
||||
$display($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION));
|
||||
$fatal;
|
||||
end
|
||||
|
||||
|
||||
void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org"));
|
||||
void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv"));
|
||||
void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GCK"));
|
||||
void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, XLEN==64 ? 56 : 34));
|
||||
void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
|
||||
|
||||
if(elffilename == "buildroot") filename = "";
|
||||
if(elffilename == "buildroot") filename = "";
|
||||
else filename = elffilename;
|
||||
|
||||
// use the ImperasDV rvviRefInit to load the reference model with an elf file
|
||||
@ -778,8 +768,8 @@ end
|
||||
if (!rvviRefInit("")) begin // still have to call with nothing
|
||||
$display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
|
||||
$fatal;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"};
|
||||
bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
|
||||
|
||||
@ -797,7 +787,7 @@ end
|
||||
//$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
|
||||
end
|
||||
$fclose(memFile);
|
||||
|
||||
|
||||
$display("RVVI Loading ram.bin");
|
||||
memFile = $fopen(memfilenameImperasDV, "rb");
|
||||
index = 'h80000000 - 8;
|
||||
@ -812,9 +802,9 @@ end
|
||||
//$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
|
||||
end
|
||||
$fclose(memFile);
|
||||
|
||||
|
||||
$display("RVVI Loading Complete");
|
||||
|
||||
|
||||
void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address
|
||||
end
|
||||
|
||||
@ -829,22 +819,22 @@ end
|
||||
void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH
|
||||
void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH
|
||||
void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH
|
||||
void'(rvviRefCsrSetVolatile(0, 32'hC81)); // TIMEH
|
||||
void'(rvviRefCsrSetVolatile(0, 32'hC81)); // TIMEH
|
||||
end
|
||||
// User HPMCOUNTER3 - HPMCOUNTER31
|
||||
for (iter='hC03; iter<='hC1F; iter++) begin
|
||||
void'(rvviRefCsrSetVolatile(0, iter)); // HPMCOUNTERx
|
||||
if (P.XLEN == 32)
|
||||
if (P.XLEN == 32)
|
||||
void'(rvviRefCsrSetVolatile(0, iter+128)); // HPMCOUNTERxH
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// Machine MHPMCOUNTER3 - MHPMCOUNTER31
|
||||
for (iter='hB03; iter<='hB1F; iter++) begin
|
||||
void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx
|
||||
if (P.XLEN == 32)
|
||||
if (P.XLEN == 32)
|
||||
void'(rvviRefCsrSetVolatile(0, iter+128)); // MHPMCOUNTERxH
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// cannot predict this register due to latency between
|
||||
// pending and taken
|
||||
void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP
|
||||
@ -880,7 +870,7 @@ end
|
||||
end
|
||||
|
||||
void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!!
|
||||
|
||||
|
||||
end
|
||||
|
||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7]));
|
||||
@ -902,7 +892,7 @@ end
|
||||
task automatic CheckSignature;
|
||||
// This task must be declared inside this module as it needs access to parameter P. There is
|
||||
// no way to pass P to the task unless we convert it to a module.
|
||||
|
||||
|
||||
input string pathname;
|
||||
input string TestName;
|
||||
input logic riscofTest;
|
||||
@ -920,8 +910,8 @@ end
|
||||
string signame;
|
||||
logic [P.XLEN-1:0] testadr, testadrNoBase;
|
||||
|
||||
//$display("Invoking CheckSignature %s %s %0t", pathname, TestName, $time);
|
||||
|
||||
//$display("Invoking CheckSignature %s %s %0t", pathname, TestName, $time);
|
||||
|
||||
// read .signature.output file and compare to check for errors
|
||||
if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
|
||||
else signame = {pathname, TestName, ".signature.output"};
|
||||
@ -951,8 +941,8 @@ end
|
||||
end
|
||||
|
||||
// Check valid number of lines were read
|
||||
if (siglines == 0) begin
|
||||
errors = 1;
|
||||
if (siglines == 0) begin
|
||||
errors = 1;
|
||||
$display("Error: empty test file %s", signame);
|
||||
end else if (P.XLEN == 64 & (siglines % 2)) begin
|
||||
errors = 1;
|
||||
@ -970,9 +960,9 @@ end
|
||||
testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
|
||||
testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
|
||||
for (i=0; i<sigentries; i++) begin
|
||||
if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin
|
||||
if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin
|
||||
errors = errors+1;
|
||||
$display(" Error on test %s result %d: adr = %h sim (D$) %h signature = %h",
|
||||
$display(" Error on test %s result %d: adr = %h sim (D$) %h signature = %h",
|
||||
TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]);
|
||||
$stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage
|
||||
end
|
||||
@ -980,7 +970,7 @@ end
|
||||
if (errors) $display("%s failed with %d errors. :(", TestName, errors);
|
||||
else $display("%s succeeded. Brilliant!!!", TestName);
|
||||
endtask
|
||||
|
||||
|
||||
`ifdef PMP_COVERAGE
|
||||
test_pmp_coverage #(P) pmp_inst(clk);
|
||||
`endif
|
||||
@ -1025,7 +1015,7 @@ task automatic updateProgramAddrLabelArray;
|
||||
returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
|
||||
if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// if(ProgramAddrLabelArray["begin_signature"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile);
|
||||
// if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile);
|
||||
|
||||
@ -24,17 +24,15 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`define IMPERASTEST "0"
|
||||
`define RISCVARCHTEST "1"
|
||||
`define WALLYTEST "2"
|
||||
`define COREMARK "3"
|
||||
`define EMBENCH "4"
|
||||
`define CUSTOM "5"
|
||||
`define COVERAGE "6"
|
||||
`define BUILDROOT "7"
|
||||
`define RISCVARCHTEST "0"
|
||||
`define WALLYTEST "1"
|
||||
`define COREMARK "2"
|
||||
`define EMBENCH "3"
|
||||
`define CUSTOM "4"
|
||||
`define COVERAGE "5"
|
||||
`define BUILDROOT "6"
|
||||
|
||||
string tvpaths[] = '{
|
||||
"$RISCV/imperas-riscv-tests/work/",
|
||||
"../../tests/riscof/work/riscv-arch-test/",
|
||||
"../../tests/riscof/work/wally-riscv-arch-test/",
|
||||
"../../benchmarks/coremark/work/",
|
||||
@ -183,745 +181,6 @@ string embench[] = '{
|
||||
"bd_sizeopt_speed/src/wikisort/wikisort"
|
||||
};
|
||||
|
||||
string imperas32f[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv32i_m/F/FSQRT-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FADD-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FADD-S-DYN-RMM-01",
|
||||
"rv32i_m/F/FADD-S-DYN-RNE-01",
|
||||
"rv32i_m/F/FADD-S-DYN-RTZ-01",
|
||||
"rv32i_m/F/FADD-S-DYN-RUP-01",
|
||||
"rv32i_m/F/FADD-S-RDN-01",
|
||||
"rv32i_m/F/FADD-S-RMM-01",
|
||||
"rv32i_m/F/FADD-S-RNE-01",
|
||||
"rv32i_m/F/FADD-S-RTZ-01",
|
||||
"rv32i_m/F/FADD-S-RUP-01",
|
||||
"rv32i_m/F/FCLASS-S-01",
|
||||
"rv32i_m/F/FCVT-S-W-DYN-RDN-01",
|
||||
"rv32i_m/F/FCVT-S-W-DYN-RMM-01",
|
||||
"rv32i_m/F/FCVT-S-W-DYN-RNE-01",
|
||||
"rv32i_m/F/FCVT-S-W-DYN-RTZ-01",
|
||||
"rv32i_m/F/FCVT-S-W-DYN-RUP-01",
|
||||
"rv32i_m/F/FCVT-S-W-RDN-01",
|
||||
"rv32i_m/F/FCVT-S-W-RMM-01",
|
||||
"rv32i_m/F/FCVT-S-W-RNE-01",
|
||||
"rv32i_m/F/FCVT-S-W-RTZ-01",
|
||||
"rv32i_m/F/FCVT-S-W-RUP-01",
|
||||
"rv32i_m/F/FCVT-S-WU-DYN-RDN-01",
|
||||
"rv32i_m/F/FCVT-S-WU-DYN-RMM-01",
|
||||
"rv32i_m/F/FCVT-S-WU-DYN-RNE-01",
|
||||
"rv32i_m/F/FCVT-S-WU-DYN-RTZ-01",
|
||||
"rv32i_m/F/FCVT-S-WU-DYN-RUP-01",
|
||||
"rv32i_m/F/FCVT-S-WU-RDN-01",
|
||||
"rv32i_m/F/FCVT-S-WU-RMM-01",
|
||||
"rv32i_m/F/FCVT-S-WU-RNE-01",
|
||||
"rv32i_m/F/FCVT-S-WU-RTZ-01",
|
||||
"rv32i_m/F/FCVT-S-WU-RUP-01",
|
||||
"rv32i_m/F/FCVT-W-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FCVT-W-S-DYN-RMM-01",
|
||||
"rv32i_m/F/FCVT-W-S-DYN-RNE-01",
|
||||
"rv32i_m/F/FCVT-W-S-DYN-RTZ-01",
|
||||
"rv32i_m/F/FCVT-W-S-DYN-RUP-01",
|
||||
"rv32i_m/F/FCVT-W-S-RDN-01",
|
||||
"rv32i_m/F/FCVT-W-S-RMM-01",
|
||||
"rv32i_m/F/FCVT-W-S-RNE-01",
|
||||
"rv32i_m/F/FCVT-W-S-RTZ-01",
|
||||
"rv32i_m/F/FCVT-W-S-RUP-01",
|
||||
"rv32i_m/F/FCVT-WU-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FCVT-WU-S-DYN-RMM-01",
|
||||
"rv32i_m/F/FCVT-WU-S-DYN-RNE-01",
|
||||
"rv32i_m/F/FCVT-WU-S-DYN-RTZ-01",
|
||||
"rv32i_m/F/FCVT-WU-S-DYN-RUP-01",
|
||||
"rv32i_m/F/FCVT-WU-S-RDN-01",
|
||||
"rv32i_m/F/FCVT-WU-S-RMM-01",
|
||||
"rv32i_m/F/FCVT-WU-S-RNE-01",
|
||||
"rv32i_m/F/FCVT-WU-S-RTZ-01",
|
||||
"rv32i_m/F/FCVT-WU-S-RUP-01",
|
||||
"rv32i_m/F/FDIV-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FDIV-S-DYN-RMM-01",
|
||||
"rv32i_m/F/FDIV-S-DYN-RNE-01",
|
||||
"rv32i_m/F/FDIV-S-DYN-RTZ-01",
|
||||
"rv32i_m/F/FDIV-S-DYN-RUP-01",
|
||||
"rv32i_m/F/FDIV-S-RDN-01",
|
||||
"rv32i_m/F/FDIV-S-RMM-01",
|
||||
"rv32i_m/F/FDIV-S-RNE-01",
|
||||
"rv32i_m/F/FDIV-S-RTZ-01",
|
||||
"rv32i_m/F/FDIV-S-RUP-01",
|
||||
"rv32i_m/F/FEQ-S-01",
|
||||
"rv32i_m/F/FLE-S-01",
|
||||
"rv32i_m/F/FLT-S-01",
|
||||
"rv32i_m/F/FLW-01",
|
||||
"rv32i_m/F/FMADD-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FMADD-S-DYN-RMM-01",
|
||||
"rv32i_m/F/FMADD-S-DYN-RNE-01",
|
||||
"rv32i_m/F/FMADD-S-DYN-RTZ-01",
|
||||
"rv32i_m/F/FMADD-S-DYN-RUP-01",
|
||||
"rv32i_m/F/FMADD-S-RDN-01",
|
||||
"rv32i_m/F/FMADD-S-RMM-01",
|
||||
"rv32i_m/F/FMADD-S-RNE-01",
|
||||
"rv32i_m/F/FMADD-S-RTZ-01",
|
||||
"rv32i_m/F/FMADD-S-RUP-01",
|
||||
"rv32i_m/F/FMAX-S-01",
|
||||
"rv32i_m/F/FMIN-S-01",
|
||||
"rv32i_m/F/FMSUB-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FMSUB-S-DYN-RMM-01",
|
||||
"rv32i_m/F/FMSUB-S-DYN-RNE-01",
|
||||
"rv32i_m/F/FMSUB-S-DYN-RTZ-01",
|
||||
"rv32i_m/F/FMSUB-S-DYN-RUP-01",
|
||||
"rv32i_m/F/FMSUB-S-RDN-01",
|
||||
"rv32i_m/F/FMSUB-S-RMM-01",
|
||||
"rv32i_m/F/FMSUB-S-RNE-01",
|
||||
"rv32i_m/F/FMSUB-S-RTZ-01",
|
||||
"rv32i_m/F/FMSUB-S-RUP-01",
|
||||
"rv32i_m/F/FMUL-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FMUL-S-DYN-RMM-01",
|
||||
"rv32i_m/F/FMUL-S-DYN-RNE-01",
|
||||
"rv32i_m/F/FMUL-S-DYN-RTZ-01",
|
||||
"rv32i_m/F/FMUL-S-DYN-RUP-01",
|
||||
"rv32i_m/F/FMUL-S-RDN-01",
|
||||
"rv32i_m/F/FMUL-S-RMM-01",
|
||||
"rv32i_m/F/FMUL-S-RNE-01",
|
||||
"rv32i_m/F/FMUL-S-RTZ-01",
|
||||
"rv32i_m/F/FMUL-S-RUP-01",
|
||||
"rv32i_m/F/FMV-W-X-01",
|
||||
"rv32i_m/F/FMV-X-W-01",
|
||||
"rv32i_m/F/FNMADD-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FNMADD-S-DYN-RMM-01",
|
||||
"rv32i_m/F/FNMADD-S-DYN-RNE-01",
|
||||
"rv32i_m/F/FNMADD-S-DYN-RTZ-01",
|
||||
"rv32i_m/F/FNMADD-S-DYN-RUP-01",
|
||||
"rv32i_m/F/FNMADD-S-RDN-01",
|
||||
"rv32i_m/F/FNMADD-S-RMM-01",
|
||||
"rv32i_m/F/FNMADD-S-RNE-01",
|
||||
"rv32i_m/F/FNMADD-S-RTZ-01",
|
||||
"rv32i_m/F/FNMADD-S-RUP-01",
|
||||
"rv32i_m/F/FNMSUB-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FNMSUB-S-DYN-RMM-01",
|
||||
"rv32i_m/F/FNMSUB-S-DYN-RNE-01",
|
||||
"rv32i_m/F/FNMSUB-S-DYN-RTZ-01",
|
||||
"rv32i_m/F/FNMSUB-S-DYN-RUP-01",
|
||||
"rv32i_m/F/FNMSUB-S-RDN-01",
|
||||
"rv32i_m/F/FNMSUB-S-RMM-01",
|
||||
"rv32i_m/F/FNMSUB-S-RNE-01",
|
||||
"rv32i_m/F/FNMSUB-S-RTZ-01",
|
||||
"rv32i_m/F/FNMSUB-S-RUP-01",
|
||||
"rv32i_m/F/FSGNJN-S-01",
|
||||
"rv32i_m/F/FSGNJ-S-01",
|
||||
"rv32i_m/F/FSGNJX-S-01",
|
||||
"rv32i_m/F/FSQRT-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FSQRT-S-DYN-RMM-01",
|
||||
"rv32i_m/F/FSQRT-S-DYN-RNE-01",
|
||||
"rv32i_m/F/FSQRT-S-DYN-RTZ-01",
|
||||
"rv32i_m/F/FSQRT-S-DYN-RUP-01",
|
||||
"rv32i_m/F/FSQRT-S-RDN-01",
|
||||
"rv32i_m/F/FSQRT-S-RMM-01",
|
||||
"rv32i_m/F/FSQRT-S-RNE-01",
|
||||
"rv32i_m/F/FSQRT-S-RTZ-01",
|
||||
"rv32i_m/F/FSQRT-S-RUP-01",
|
||||
"rv32i_m/F/FSUB-S-DYN-RDN-01",
|
||||
"rv32i_m/F/FSUB-S-DYN-RMM-01",
|
||||
"rv32i_m/F/FSUB-S-DYN-RNE-01",
|
||||
"rv32i_m/F/FSUB-S-DYN-RTZ-01",
|
||||
"rv32i_m/F/FSUB-S-DYN-RUP-01",
|
||||
"rv32i_m/F/FSUB-S-RDN-01",
|
||||
"rv32i_m/F/FSUB-S-RMM-01",
|
||||
"rv32i_m/F/FSUB-S-RNE-01",
|
||||
"rv32i_m/F/FSUB-S-RTZ-01",
|
||||
"rv32i_m/F/FSUB-S-RUP-01",
|
||||
"rv32i_m/F/FSW-01"
|
||||
};
|
||||
|
||||
string imperas64f[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64i_m/F/FADD-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FADD-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FADD-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FADD-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FADD-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FADD-S-RDN-01",
|
||||
"rv64i_m/F/FADD-S-RMM-01",
|
||||
"rv64i_m/F/FADD-S-RNE-01",
|
||||
"rv64i_m/F/FADD-S-RTZ-01",
|
||||
"rv64i_m/F/FADD-S-RUP-01",
|
||||
"rv64i_m/F/FCLASS-S-01",
|
||||
"rv64i_m/F/FCVT-L-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FCVT-L-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FCVT-L-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FCVT-L-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FCVT-L-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FCVT-L-S-RDN-01",
|
||||
"rv64i_m/F/FCVT-L-S-RMM-01",
|
||||
"rv64i_m/F/FCVT-L-S-RNE-01",
|
||||
"rv64i_m/F/FCVT-L-S-RTZ-01",
|
||||
"rv64i_m/F/FCVT-L-S-RUP-01",
|
||||
"rv64i_m/F/FCVT-LU-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FCVT-LU-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FCVT-LU-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FCVT-LU-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FCVT-LU-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FCVT-LU-S-RDN-01",
|
||||
"rv64i_m/F/FCVT-LU-S-RMM-01",
|
||||
"rv64i_m/F/FCVT-LU-S-RNE-01",
|
||||
"rv64i_m/F/FCVT-LU-S-RTZ-01",
|
||||
"rv64i_m/F/FCVT-LU-S-RUP-01",
|
||||
"rv64i_m/F/FCVT-S-L-DYN-RDN-01",
|
||||
"rv64i_m/F/FCVT-S-L-DYN-RMM-01",
|
||||
"rv64i_m/F/FCVT-S-L-DYN-RNE-01",
|
||||
"rv64i_m/F/FCVT-S-L-DYN-RTZ-01",
|
||||
"rv64i_m/F/FCVT-S-L-DYN-RUP-01",
|
||||
"rv64i_m/F/FCVT-S-L-RDN-01",
|
||||
"rv64i_m/F/FCVT-S-L-RMM-01",
|
||||
"rv64i_m/F/FCVT-S-L-RNE-01",
|
||||
"rv64i_m/F/FCVT-S-L-RTZ-01",
|
||||
"rv64i_m/F/FCVT-S-L-RUP-01",
|
||||
"rv64i_m/F/FCVT-S-LU-DYN-RDN-01",
|
||||
"rv64i_m/F/FCVT-S-LU-DYN-RMM-01",
|
||||
"rv64i_m/F/FCVT-S-LU-DYN-RNE-01",
|
||||
"rv64i_m/F/FCVT-S-LU-DYN-RTZ-01",
|
||||
"rv64i_m/F/FCVT-S-LU-DYN-RUP-01",
|
||||
"rv64i_m/F/FCVT-S-LU-RDN-01",
|
||||
"rv64i_m/F/FCVT-S-LU-RMM-01",
|
||||
"rv64i_m/F/FCVT-S-LU-RNE-01",
|
||||
"rv64i_m/F/FCVT-S-LU-RTZ-01",
|
||||
"rv64i_m/F/FCVT-S-LU-RUP-01",
|
||||
"rv64i_m/F/FCVT-S-W-DYN-RDN-01",
|
||||
"rv64i_m/F/FCVT-S-W-DYN-RMM-01",
|
||||
"rv64i_m/F/FCVT-S-W-DYN-RNE-01",
|
||||
"rv64i_m/F/FCVT-S-W-DYN-RTZ-01",
|
||||
"rv64i_m/F/FCVT-S-W-DYN-RUP-01",
|
||||
"rv64i_m/F/FCVT-S-W-RDN-01",
|
||||
"rv64i_m/F/FCVT-S-W-RMM-01",
|
||||
"rv64i_m/F/FCVT-S-W-RNE-01",
|
||||
"rv64i_m/F/FCVT-S-W-RTZ-01",
|
||||
"rv64i_m/F/FCVT-S-W-RUP-01",
|
||||
"rv64i_m/F/FCVT-S-WU-DYN-RDN-01",
|
||||
"rv64i_m/F/FCVT-S-WU-DYN-RMM-01",
|
||||
"rv64i_m/F/FCVT-S-WU-DYN-RNE-01",
|
||||
"rv64i_m/F/FCVT-S-WU-DYN-RTZ-01",
|
||||
"rv64i_m/F/FCVT-S-WU-DYN-RUP-01",
|
||||
"rv64i_m/F/FCVT-S-WU-RDN-01",
|
||||
"rv64i_m/F/FCVT-S-WU-RMM-01",
|
||||
"rv64i_m/F/FCVT-S-WU-RNE-01",
|
||||
"rv64i_m/F/FCVT-S-WU-RTZ-01",
|
||||
"rv64i_m/F/FCVT-S-WU-RUP-01",
|
||||
"rv64i_m/F/FCVT-W-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FCVT-W-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FCVT-W-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FCVT-W-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FCVT-W-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FCVT-W-S-RDN-01",
|
||||
"rv64i_m/F/FCVT-W-S-RMM-01",
|
||||
"rv64i_m/F/FCVT-W-S-RNE-01",
|
||||
"rv64i_m/F/FCVT-W-S-RTZ-01",
|
||||
"rv64i_m/F/FCVT-W-S-RUP-01",
|
||||
"rv64i_m/F/FCVT-WU-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FCVT-WU-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FCVT-WU-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FCVT-WU-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FCVT-WU-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FCVT-WU-S-RDN-01",
|
||||
"rv64i_m/F/FCVT-WU-S-RMM-01",
|
||||
"rv64i_m/F/FCVT-WU-S-RNE-01",
|
||||
"rv64i_m/F/FCVT-WU-S-RTZ-01",
|
||||
"rv64i_m/F/FCVT-WU-S-RUP-01",
|
||||
"rv64i_m/F/FDIV-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FDIV-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FDIV-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FDIV-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FDIV-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FDIV-S-RDN-01",
|
||||
"rv64i_m/F/FDIV-S-RMM-01",
|
||||
"rv64i_m/F/FDIV-S-RNE-01",
|
||||
"rv64i_m/F/FDIV-S-RTZ-01",
|
||||
"rv64i_m/F/FDIV-S-RUP-01",
|
||||
"rv64i_m/F/FEQ-S-01",
|
||||
"rv64i_m/F/FLE-S-01",
|
||||
"rv64i_m/F/FLT-S-01",
|
||||
"rv64i_m/F/FLW-01",
|
||||
"rv64i_m/F/FMADD-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FMADD-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FMADD-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FMADD-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FMADD-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FMADD-S-RDN-01",
|
||||
"rv64i_m/F/FMADD-S-RMM-01",
|
||||
"rv64i_m/F/FMADD-S-RNE-01",
|
||||
"rv64i_m/F/FMADD-S-RTZ-01",
|
||||
"rv64i_m/F/FMADD-S-RUP-01",
|
||||
"rv64i_m/F/FMAX-S-01",
|
||||
"rv64i_m/F/FMIN-S-01",
|
||||
"rv64i_m/F/FMSUB-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FMSUB-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FMSUB-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FMSUB-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FMSUB-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FMSUB-S-RDN-01",
|
||||
"rv64i_m/F/FMSUB-S-RMM-01",
|
||||
"rv64i_m/F/FMSUB-S-RNE-01",
|
||||
"rv64i_m/F/FMSUB-S-RTZ-01",
|
||||
"rv64i_m/F/FMSUB-S-RUP-01",
|
||||
"rv64i_m/F/FMUL-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FMUL-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FMUL-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FMUL-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FMUL-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FMUL-S-RDN-01",
|
||||
"rv64i_m/F/FMUL-S-RMM-01",
|
||||
"rv64i_m/F/FMUL-S-RNE-01",
|
||||
"rv64i_m/F/FMUL-S-RTZ-01",
|
||||
"rv64i_m/F/FMUL-S-RUP-01",
|
||||
"rv64i_m/F/FMV-W-X-01",
|
||||
"rv64i_m/F/FMV-X-W-01",
|
||||
"rv64i_m/F/FNMADD-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FNMADD-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FNMADD-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FNMADD-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FNMADD-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FNMADD-S-RDN-01",
|
||||
"rv64i_m/F/FNMADD-S-RMM-01",
|
||||
"rv64i_m/F/FNMADD-S-RNE-01",
|
||||
"rv64i_m/F/FNMADD-S-RTZ-01",
|
||||
"rv64i_m/F/FNMADD-S-RUP-01",
|
||||
"rv64i_m/F/FNMSUB-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FNMSUB-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FNMSUB-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FNMSUB-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FNMSUB-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FNMSUB-S-RDN-01",
|
||||
"rv64i_m/F/FNMSUB-S-RMM-01",
|
||||
"rv64i_m/F/FNMSUB-S-RNE-01",
|
||||
"rv64i_m/F/FNMSUB-S-RTZ-01",
|
||||
"rv64i_m/F/FNMSUB-S-RUP-01",
|
||||
"rv64i_m/F/FSGNJN-S-01",
|
||||
"rv64i_m/F/FSGNJ-S-01",
|
||||
"rv64i_m/F/FSGNJX-S-01",
|
||||
"rv64i_m/F/FSQRT-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FSQRT-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FSQRT-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FSQRT-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FSQRT-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FSQRT-S-RDN-01",
|
||||
"rv64i_m/F/FSQRT-S-RMM-01",
|
||||
"rv64i_m/F/FSQRT-S-RNE-01",
|
||||
"rv64i_m/F/FSQRT-S-RTZ-01",
|
||||
"rv64i_m/F/FSQRT-S-RUP-01",
|
||||
"rv64i_m/F/FSUB-S-DYN-RDN-01",
|
||||
"rv64i_m/F/FSUB-S-DYN-RMM-01",
|
||||
"rv64i_m/F/FSUB-S-DYN-RNE-01",
|
||||
"rv64i_m/F/FSUB-S-DYN-RTZ-01",
|
||||
"rv64i_m/F/FSUB-S-DYN-RUP-01",
|
||||
"rv64i_m/F/FSUB-S-RDN-01",
|
||||
"rv64i_m/F/FSUB-S-RMM-01",
|
||||
"rv64i_m/F/FSUB-S-RNE-01",
|
||||
"rv64i_m/F/FSUB-S-RTZ-01",
|
||||
"rv64i_m/F/FSUB-S-RUP-01",
|
||||
"rv64i_m/F/FSW-01"
|
||||
};
|
||||
|
||||
string imperas64d[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64i_m/D/FADD-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FADD-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FADD-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FADD-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FADD-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FADD-D-RDN-01",
|
||||
"rv64i_m/D/FADD-D-RMM-01",
|
||||
"rv64i_m/D/FADD-D-RNE-01",
|
||||
"rv64i_m/D/FADD-D-RTZ-01",
|
||||
"rv64i_m/D/FADD-D-RUP-01",
|
||||
"rv64i_m/D/FCLASS-D-01",
|
||||
"rv64i_m/D/FCVT-D-L-DYN-RDN-01",
|
||||
"rv64i_m/D/FCVT-D-L-DYN-RMM-01",
|
||||
"rv64i_m/D/FCVT-D-L-DYN-RNE-01",
|
||||
"rv64i_m/D/FCVT-D-L-DYN-RTZ-01",
|
||||
"rv64i_m/D/FCVT-D-L-DYN-RUP-01",
|
||||
"rv64i_m/D/FCVT-D-L-RDN-01",
|
||||
"rv64i_m/D/FCVT-D-L-RMM-01",
|
||||
"rv64i_m/D/FCVT-D-L-RNE-01",
|
||||
"rv64i_m/D/FCVT-D-L-RTZ-01",
|
||||
"rv64i_m/D/FCVT-D-L-RUP-01",
|
||||
"rv64i_m/D/FCVT-D-LU-DYN-RDN-01",
|
||||
"rv64i_m/D/FCVT-D-LU-DYN-RMM-01",
|
||||
"rv64i_m/D/FCVT-D-LU-DYN-RNE-01",
|
||||
"rv64i_m/D/FCVT-D-LU-DYN-RTZ-01",
|
||||
"rv64i_m/D/FCVT-D-LU-DYN-RUP-01",
|
||||
"rv64i_m/D/FCVT-D-LU-RDN-01",
|
||||
"rv64i_m/D/FCVT-D-LU-RMM-01",
|
||||
"rv64i_m/D/FCVT-D-LU-RNE-01",
|
||||
"rv64i_m/D/FCVT-D-LU-RTZ-01",
|
||||
"rv64i_m/D/FCVT-D-LU-RUP-01",
|
||||
"rv64i_m/D/FCVT-D-S-01",
|
||||
"rv64i_m/D/FCVT-D-W-01",
|
||||
"rv64i_m/D/FCVT-D-WU-01",
|
||||
"rv64i_m/D/FCVT-L-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FCVT-L-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FCVT-L-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FCVT-L-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FCVT-L-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FCVT-L-D-RDN-01",
|
||||
"rv64i_m/D/FCVT-L-D-RMM-01",
|
||||
"rv64i_m/D/FCVT-L-D-RNE-01",
|
||||
"rv64i_m/D/FCVT-L-D-RTZ-01",
|
||||
"rv64i_m/D/FCVT-L-D-RUP-01",
|
||||
"rv64i_m/D/FCVT-LU-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FCVT-LU-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FCVT-LU-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FCVT-LU-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FCVT-LU-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FCVT-LU-D-RDN-01",
|
||||
"rv64i_m/D/FCVT-LU-D-RMM-01",
|
||||
"rv64i_m/D/FCVT-LU-D-RNE-01",
|
||||
"rv64i_m/D/FCVT-LU-D-RTZ-01",
|
||||
"rv64i_m/D/FCVT-LU-D-RUP-01",
|
||||
"rv64i_m/D/FCVT-S-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FCVT-S-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FCVT-S-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FCVT-S-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FCVT-S-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FCVT-S-D-RDN-01",
|
||||
"rv64i_m/D/FCVT-S-D-RMM-01",
|
||||
"rv64i_m/D/FCVT-S-D-RNE-01",
|
||||
"rv64i_m/D/FCVT-S-D-RTZ-01",
|
||||
"rv64i_m/D/FCVT-S-D-RUP-01",
|
||||
"rv64i_m/D/FCVT-W-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FCVT-W-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FCVT-W-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FCVT-W-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FCVT-W-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FCVT-W-D-RDN-01",
|
||||
"rv64i_m/D/FCVT-W-D-RMM-01",
|
||||
"rv64i_m/D/FCVT-W-D-RNE-01",
|
||||
"rv64i_m/D/FCVT-W-D-RTZ-01",
|
||||
"rv64i_m/D/FCVT-W-D-RUP-01",
|
||||
"rv64i_m/D/FCVT-WU-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FCVT-WU-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FCVT-WU-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FCVT-WU-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FCVT-WU-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FCVT-WU-D-RDN-01",
|
||||
"rv64i_m/D/FCVT-WU-D-RMM-01",
|
||||
"rv64i_m/D/FCVT-WU-D-RNE-01",
|
||||
"rv64i_m/D/FCVT-WU-D-RTZ-01",
|
||||
"rv64i_m/D/FCVT-WU-D-RUP-01",
|
||||
"rv64i_m/D/FDIV-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FDIV-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FDIV-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FDIV-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FDIV-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FDIV-D-RDN-01",
|
||||
"rv64i_m/D/FDIV-D-RMM-01",
|
||||
"rv64i_m/D/FDIV-D-RNE-01",
|
||||
"rv64i_m/D/FDIV-D-RTZ-01",
|
||||
"rv64i_m/D/FDIV-D-RUP-01",
|
||||
"rv64i_m/D/FEQ-D-01",
|
||||
"rv64i_m/D/FLD-01",
|
||||
"rv64i_m/D/FLE-D-01",
|
||||
"rv64i_m/D/FLT-D-01",
|
||||
"rv64i_m/D/FMADD-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FMADD-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FMADD-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FMADD-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FMADD-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FMADD-D-RDN-01",
|
||||
"rv64i_m/D/FMADD-D-RMM-01",
|
||||
"rv64i_m/D/FMADD-D-RNE-01",
|
||||
"rv64i_m/D/FMADD-D-RTZ-01",
|
||||
"rv64i_m/D/FMADD-D-RUP-01",
|
||||
"rv64i_m/D/FMAX-D-01",
|
||||
"rv64i_m/D/FMIN-D-01",
|
||||
"rv64i_m/D/FMSUB-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FMSUB-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FMSUB-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FMSUB-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FMSUB-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FMSUB-D-RDN-01",
|
||||
"rv64i_m/D/FMSUB-D-RMM-01",
|
||||
"rv64i_m/D/FMSUB-D-RNE-01",
|
||||
"rv64i_m/D/FMSUB-D-RTZ-01",
|
||||
"rv64i_m/D/FMSUB-D-RUP-01",
|
||||
"rv64i_m/D/FMUL-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FMUL-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FMUL-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FMUL-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FMUL-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FMUL-D-RDN-01",
|
||||
"rv64i_m/D/FMUL-D-RMM-01",
|
||||
"rv64i_m/D/FMUL-D-RNE-01",
|
||||
"rv64i_m/D/FMUL-D-RTZ-01",
|
||||
"rv64i_m/D/FMUL-D-RUP-01",
|
||||
"rv64i_m/D/FMV-D-X-01",
|
||||
"rv64i_m/D/FMV-X-D-01",
|
||||
"rv64i_m/D/FNMADD-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FNMADD-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FNMADD-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FNMADD-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FNMADD-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FNMADD-D-RDN-01",
|
||||
"rv64i_m/D/FNMADD-D-RMM-01",
|
||||
"rv64i_m/D/FNMADD-D-RNE-01",
|
||||
"rv64i_m/D/FNMADD-D-RTZ-01",
|
||||
"rv64i_m/D/FNMADD-D-RUP-01",
|
||||
"rv64i_m/D/FNMSUB-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FNMSUB-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FNMSUB-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FNMSUB-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FNMSUB-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FNMSUB-D-RDN-01",
|
||||
"rv64i_m/D/FNMSUB-D-RMM-01",
|
||||
"rv64i_m/D/FNMSUB-D-RNE-01",
|
||||
"rv64i_m/D/FNMSUB-D-RTZ-01",
|
||||
"rv64i_m/D/FNMSUB-D-RUP-01",
|
||||
"rv64i_m/D/FSD-01",
|
||||
"rv64i_m/D/FSGNJ-D-01",
|
||||
"rv64i_m/D/FSGNJN-D-01",
|
||||
"rv64i_m/D/FSGNJX-D-01",
|
||||
"rv64i_m/D/FSQRT-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FSQRT-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FSQRT-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FSQRT-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FSQRT-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FSQRT-D-RDN-01",
|
||||
"rv64i_m/D/FSQRT-D-RMM-01",
|
||||
"rv64i_m/D/FSQRT-D-RNE-01",
|
||||
"rv64i_m/D/FSQRT-D-RTZ-01",
|
||||
"rv64i_m/D/FSQRT-D-RUP-01",
|
||||
"rv64i_m/D/FSUB-D-DYN-RDN-01",
|
||||
"rv64i_m/D/FSUB-D-DYN-RMM-01",
|
||||
"rv64i_m/D/FSUB-D-DYN-RNE-01",
|
||||
"rv64i_m/D/FSUB-D-DYN-RTZ-01",
|
||||
"rv64i_m/D/FSUB-D-DYN-RUP-01",
|
||||
"rv64i_m/D/FSUB-D-RDN-01",
|
||||
"rv64i_m/D/FSUB-D-RMM-01",
|
||||
"rv64i_m/D/FSUB-D-RNE-01",
|
||||
"rv64i_m/D/FSUB-D-RTZ-01",
|
||||
"rv64i_m/D/FSUB-D-RUP-01"
|
||||
};
|
||||
|
||||
string imperas64m[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64i_m/M/DIV-01",
|
||||
"rv64i_m/M/DIVU-01",
|
||||
"rv64i_m/M/DIVUW-01",
|
||||
"rv64i_m/M/DIVW-01",
|
||||
"rv64i_m/M/MUL-01",
|
||||
"rv64i_m/M/MULH-01",
|
||||
"rv64i_m/M/MULHSU-01",
|
||||
"rv64i_m/M/MULHU-01",
|
||||
"rv64i_m/M/MULW-01",
|
||||
"rv64i_m/M/REM-01",
|
||||
"rv64i_m/M/REMU-01",
|
||||
"rv64i_m/M/REMUW-01",
|
||||
"rv64i_m/M/REMW-01"
|
||||
};
|
||||
|
||||
string imperas64c[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64i_m/C/C-ADD-01",
|
||||
"rv64i_m/C/C-ADDI-01",
|
||||
"rv64i_m/C/C-ADDI16SP-01",
|
||||
"rv64i_m/C/C-ADDI4SPN-01",
|
||||
"rv64i_m/C/C-ADDIW-01",
|
||||
"rv64i_m/C/C-ADDW-01",
|
||||
"rv64i_m/C/C-AND-01",
|
||||
"rv64i_m/C/C-ANDI-01",
|
||||
"rv64i_m/C/C-BEQZ-01",
|
||||
"rv64i_m/C/C-BNEZ-01",
|
||||
"rv64i_m/C/C-J-01",
|
||||
"rv64i_m/C/C-JALR-01",
|
||||
"rv64i_m/C/C-JR-01",
|
||||
"rv64i_m/C/C-LD-01",
|
||||
"rv64i_m/C/C-LDSP-01",
|
||||
"rv64i_m/C/C-LI-01",
|
||||
"rv64i_m/C/C-LUI-01",
|
||||
"rv64i_m/C/C-LW-01",
|
||||
"rv64i_m/C/C-LWSP-01",
|
||||
"rv64i_m/C/C-MV-01",
|
||||
"rv64i_m/C/C-OR-01",
|
||||
"rv64i_m/C/C-SD-01",
|
||||
"rv64i_m/C/C-SDSP-01",
|
||||
"rv64i_m/C/C-SLLI-01",
|
||||
"rv64i_m/C/C-SRAI-01",
|
||||
"rv64i_m/C/C-SRLI-01",
|
||||
"rv64i_m/C/C-SUB-01",
|
||||
"rv64i_m/C/C-SUBW-01",
|
||||
"rv64i_m/C/C-SW-01",
|
||||
"rv64i_m/C/C-SWSP-01",
|
||||
"rv64i_m/C/C-XOR-01",
|
||||
"rv64i_m/C/I-C-EBREAK-01",
|
||||
"rv64i_m/C/I-C-NOP-01"
|
||||
};
|
||||
|
||||
string imperas64iNOc[] = {
|
||||
`IMPERASTEST,
|
||||
"rv64i_m/I/I-MISALIGN_JMP-01"
|
||||
};
|
||||
|
||||
string imperas64i[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64i_m/I/I-DELAY_SLOTS-01",
|
||||
"rv64i_m/I/ADD-01",
|
||||
"rv64i_m/I/ADDI-01",
|
||||
"rv64i_m/I/ADDIW-01",
|
||||
"rv64i_m/I/ADDW-01",
|
||||
"rv64i_m/I/AND-01",
|
||||
"rv64i_m/I/ANDI-01",
|
||||
"rv64i_m/I/AUIPC-01",
|
||||
"rv64i_m/I/BEQ-01",
|
||||
"rv64i_m/I/BGE-01",
|
||||
"rv64i_m/I/BGEU-01",
|
||||
"rv64i_m/I/BLT-01",
|
||||
"rv64i_m/I/BLTU-01",
|
||||
"rv64i_m/I/BNE-01",
|
||||
"rv64i_m/I/I-DELAY_SLOTS-01",
|
||||
"rv64i_m/I/I-EBREAK-01",
|
||||
"rv64i_m/I/I-ECALL-01",
|
||||
"rv64i_m/I/I-ENDIANESS-01",
|
||||
"rv64i_m/I/I-IO-01",
|
||||
// "rv64i_m/I/I-MISALIGN_JMP-01",
|
||||
"rv64i_m/I/I-MISALIGN_LDST-01",
|
||||
"rv64i_m/I/I-NOP-01",
|
||||
"rv64i_m/I/I-RF_size-01",
|
||||
"rv64i_m/I/I-RF_width-01",
|
||||
"rv64i_m/I/I-RF_x0-01",
|
||||
"rv64i_m/I/JAL-01",
|
||||
"rv64i_m/I/JALR-01",
|
||||
"rv64i_m/I/LB-01",
|
||||
"rv64i_m/I/LBU-01",
|
||||
"rv64i_m/I/LD-01",
|
||||
"rv64i_m/I/LH-01",
|
||||
"rv64i_m/I/LHU-01",
|
||||
"rv64i_m/I/LUI-01",
|
||||
"rv64i_m/I/LW-01",
|
||||
"rv64i_m/I/LWU-01",
|
||||
"rv64i_m/I/OR-01",
|
||||
"rv64i_m/I/ORI-01",
|
||||
"rv64i_m/I/SB-01",
|
||||
"rv64i_m/I/SD-01",
|
||||
"rv64i_m/I/SH-01",
|
||||
"rv64i_m/I/SLL-01",
|
||||
"rv64i_m/I/SLLI-01",
|
||||
"rv64i_m/I/SLLIW-01",
|
||||
"rv64i_m/I/SLLW-01",
|
||||
"rv64i_m/I/SLT-01",
|
||||
"rv64i_m/I/SLTI-01",
|
||||
"rv64i_m/I/SLTIU-01",
|
||||
"rv64i_m/I/SLTU-01",
|
||||
"rv64i_m/I/SRA-01",
|
||||
"rv64i_m/I/SRAI-01",
|
||||
"rv64i_m/I/SRAIW-01",
|
||||
"rv64i_m/I/SRAW-01",
|
||||
"rv64i_m/I/SRL-01",
|
||||
"rv64i_m/I/SRLI-01",
|
||||
"rv64i_m/I/SRLIW-01",
|
||||
"rv64i_m/I/SRLW-01",
|
||||
"rv64i_m/I/SUB-01",
|
||||
"rv64i_m/I/SUBW-01",
|
||||
"rv64i_m/I/SW-01",
|
||||
"rv64i_m/I/XOR-01",
|
||||
"rv64i_m/I/XORI-01"
|
||||
};
|
||||
|
||||
string imperas32m[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv32i_m/M/DIV-01",
|
||||
"rv32i_m/M/DIVU-01",
|
||||
"rv32i_m/M/MUL-01",
|
||||
"rv32i_m/M/MULH-01",
|
||||
"rv32i_m/M/MULHSU-01",
|
||||
"rv32i_m/M/MULHU-01",
|
||||
"rv32i_m/M/REM-01",
|
||||
"rv32i_m/M/REMU-01"
|
||||
};
|
||||
|
||||
string imperas32c[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv32i_m/C/C-ADD-01",
|
||||
"rv32i_m/C/C-ADDI-01",
|
||||
"rv32i_m/C/C-ADDI16SP-01",
|
||||
"rv32i_m/C/C-ADDI4SPN-01",
|
||||
"rv32i_m/C/C-AND-01",
|
||||
"rv32i_m/C/C-ANDI-01",
|
||||
"rv32i_m/C/C-BEQZ-01",
|
||||
"rv32i_m/C/C-BNEZ-01",
|
||||
"rv32i_m/C/C-J-01",
|
||||
"rv32i_m/C/C-JAL-01",
|
||||
"rv32i_m/C/C-JALR-01",
|
||||
"rv32i_m/C/C-JR-01",
|
||||
"rv32i_m/C/C-LI-01",
|
||||
"rv32i_m/C/C-LUI-01",
|
||||
"rv32i_m/C/C-LW-01",
|
||||
"rv32i_m/C/C-LWSP-01",
|
||||
"rv32i_m/C/C-MV-01",
|
||||
"rv32i_m/C/C-OR-01",
|
||||
"rv32i_m/C/C-SLLI-01",
|
||||
"rv32i_m/C/C-SRAI-01",
|
||||
"rv32i_m/C/C-SRLI-01",
|
||||
"rv32i_m/C/C-SUB-01",
|
||||
"rv32i_m/C/C-SW-01",
|
||||
"rv32i_m/C/C-SWSP-01",
|
||||
"rv32i_m/C/C-XOR-01",
|
||||
"rv32i_m/C/I-C-EBREAK-01",
|
||||
"rv32i_m/C/I-C-NOP-01"
|
||||
};
|
||||
|
||||
string imperas32iNOc[] = {
|
||||
`IMPERASTEST,
|
||||
"rv32i_m/I/I-MISALIGN_JMP-01"
|
||||
};
|
||||
|
||||
string imperas32i[] = {
|
||||
`IMPERASTEST,
|
||||
"rv32i_m/I/ADD-01",
|
||||
"rv32i_m/I/ADDI-01",
|
||||
"rv32i_m/I/AND-01",
|
||||
"rv32i_m/I/ANDI-01",
|
||||
"rv32i_m/I/AUIPC-01",
|
||||
"rv32i_m/I/BEQ-01",
|
||||
"rv32i_m/I/BGE-01",
|
||||
"rv32i_m/I/BGEU-01",
|
||||
"rv32i_m/I/BLT-01",
|
||||
"rv32i_m/I/BLTU-01",
|
||||
"rv32i_m/I/BNE-01",
|
||||
"rv32i_m/I/I-DELAY_SLOTS-01",
|
||||
"rv32i_m/I/I-EBREAK-01",
|
||||
"rv32i_m/I/I-ECALL-01",
|
||||
"rv32i_m/I/I-ENDIANESS-01",
|
||||
"rv32i_m/I/I-IO-01",
|
||||
// "rv32i_m/I/I-MISALIGN_JMP-01",
|
||||
"rv32i_m/I/I-MISALIGN_LDST-01",
|
||||
"rv32i_m/I/I-NOP-01",
|
||||
"rv32i_m/I/I-RF_size-01",
|
||||
"rv32i_m/I/I-RF_width-01",
|
||||
"rv32i_m/I/I-RF_x0-01",
|
||||
"rv32i_m/I/JAL-01",
|
||||
"rv32i_m/I/JALR-01",
|
||||
"rv32i_m/I/LB-01",
|
||||
"rv32i_m/I/LBU-01",
|
||||
"rv32i_m/I/LH-01",
|
||||
"rv32i_m/I/LHU-01",
|
||||
"rv32i_m/I/LUI-01",
|
||||
"rv32i_m/I/LW-01",
|
||||
"rv32i_m/I/OR-01",
|
||||
"rv32i_m/I/ORI-01",
|
||||
"rv32i_m/I/SB-01",
|
||||
"rv32i_m/I/SH-01",
|
||||
"rv32i_m/I/SLL-01",
|
||||
"rv32i_m/I/SLLI-01",
|
||||
"rv32i_m/I/SLT-01",
|
||||
"rv32i_m/I/SLTI-01",
|
||||
"rv32i_m/I/SLTIU-01",
|
||||
"rv32i_m/I/SLTU-01",
|
||||
"rv32i_m/I/SRA-01",
|
||||
"rv32i_m/I/SRAI-01",
|
||||
"rv32i_m/I/SRL-01",
|
||||
"rv32i_m/I/SRLI-01",
|
||||
"rv32i_m/I/SUB-01",
|
||||
"rv32i_m/I/SW-01",
|
||||
"rv32i_m/I/XOR-01",
|
||||
"rv32i_m/I/XORI-01"
|
||||
};
|
||||
|
||||
string wally64q[] = '{
|
||||
`WALLYTEST,
|
||||
"rv64i_m/Q/src/WALLY-q-01.S"
|
||||
@ -4017,6 +3276,12 @@ string arch32c[] = '{
|
||||
"rv32i_m/C/src/cxor-01.S"
|
||||
};
|
||||
|
||||
string arch32c_misalign[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/C/src/misalign1-cjalr-01.S",
|
||||
"rv32i_m/C/src/misalign1-cjr-01.S"
|
||||
};
|
||||
|
||||
string arch32cpriv[] = '{
|
||||
// `RISCVARCHTEST,
|
||||
"rv32i_m/C/src/cebreak-01.S"
|
||||
@ -4231,17 +3496,6 @@ string custom[] = '{
|
||||
"cacheTest"
|
||||
};
|
||||
|
||||
string testsBP64[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64BP/simple"
|
||||
// "rv64BP/mmm",
|
||||
// "rv64BP/linpack_bench",
|
||||
// "rv64BP/sieve",
|
||||
// "rv64BP/qsort",
|
||||
// "rv64BP/dhrystone"
|
||||
};
|
||||
|
||||
|
||||
string ahb64[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/F/src/fadd_b11-01.S"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user