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Removing obsolete ***

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This commit is contained in:
David Harris 2024-11-20 07:23:51 -08:00
parent 3e45ef4dff
commit 028ffe9f4a
12 changed files with 20 additions and 21 deletions
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1
config/rv32e/config.vh
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@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 0;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;

1
config/rv32gc/config.vh
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@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 0;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;

1
config/rv32i/config.vh
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@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 1;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;

1
config/rv32imc/config.vh
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@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 1;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;

1
config/rv64gc/config.vh
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@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 0;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;

1
config/rv64i/config.vh
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@ -147,7 +147,6 @@ localparam WFI_TIMEOUT_BIT = 32'd16;
// Peripheral Physical Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
localparam logic DTIM_SUPPORTED = 1;
localparam logic [63:0] DTIM_BASE = 64'h80000000;
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;

2
examples/fp/fpcalc/fpcalc.c
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@ -237,7 +237,7 @@ __uint128_t parseNum(char *num) {
if (strlen(num) < 8) size = 2;
else if (strlen(num) < 16) size = 4;
else if (strlen(num) < 32) size = 8;
else if (strlen(num) < 35) size = 16; // *** will need to increase
else if (strlen(num) < 35) size = 16;
else {
printf("Error: only half, single, double, or quad precision supported");
exit(1);

2
testbench/common/functionName.sv
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@ -70,7 +70,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
begin
if ( pc == 0 ) begin
// *** want to keep the old value for mid and minval
// want to keep the old value for mid and minval
mid = 0;
return;
end

9
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output
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@ -1,4 +1,13 @@
0000000b # Test 5.2.3.6: ecall from going to S mode from M mode
00000002 # S mode write to mstatush with illegal instruction
00000002 # S mode read from mstatush with illegal instruction
00000bad
00000002 # S mode write to menvcfgh with illegal instruction
00000002 # S mode read from menvcfgh with illegal instruction
00000bad
00000002 # S mode write to mseccfgh with illegal instruction
00000002 # S mode read from mseccfgh with illegal instruction
00000bad
00000002 # S mode write to pmpcfg1 with illegal instruction
00000002 # S mode read from pmpcfg1 with illegal instruction
00000bad

11
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
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@ -117,7 +117,7 @@ cause_store_acc:
ret
cause_ecall:
// *** ASSUMES you have already gone to the mode you need to call this from.
// ASSUMES you have already gone to the mode you need to call this from.
ecall
ret
@ -319,7 +319,7 @@ end_trap_triggers:
.align 6
trap_handler_\MODE\():
j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
// ASSUMES that a cause value of 0 for an interrupt is unimplemented
// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
@ -337,7 +337,7 @@ trap_handler_\MODE\():
trap_unvectored_\MODE\():
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
// *** NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests
// NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests
trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there
// save registers on stack before using
@ -707,7 +707,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
.endm
.macro READ32 ADDR
// Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value
// Attempt read at ADDR. Write the value read out to the output. Consider adding specific test for reading a non known value
// Success outputs:
// value read out from ADDR
// Fault outputs:
@ -751,7 +751,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
// 0x9: test called from S mode
// 0xB: test called from M mode
// they generally do not fault or cause issues as long as these modes are enabled
// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
.macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
li a0, 2 // determine trap handler behavior (go to machine mode)
@ -807,7 +806,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
// value read back out from CSR after writing
// Fault outputs:
// The previous CSR value before write attempt
// *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access
// Most likely 0x2, the mcause for illegal instruction if we don't have write or read access
li t5, 0xbad // load bad value to be overwritten by csrr
li t4, \VAL
csrw \CSR\(), t4

9
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S
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@ -32,18 +32,15 @@ TRAP_HANDLER m
# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode.
# *** several of these appear not to be implemented in the assembler?
# I get "assembler messages: error: unkown CSR" with many of them.
GOTO_S_MODE 0x0, 0x0
# Attempt to write 0x111 to each of these CSRs and read the value back
# should result in an illegal instruction for the write and read, respectively
# High-bit versions storing the upper 32 bits of some CSRs for RV32
# WRITE_READ_CSR mstatush 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR menvcfgh 0x111
# WRITE_READ_CSR mseccfgh 0x111
WRITE_READ_CSR mstatush 0x111 # not supported in rv32
WRITE_READ_CSR menvcfgh 0x111
WRITE_READ_CSR mseccfgh 0x111
WRITE_READ_CSR pmpcfg1 0x111
WRITE_READ_CSR pmpcfg3 0x111
WRITE_READ_CSR mcycleh 0x111

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
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@ -66,7 +66,7 @@ test_cases:
# ---------------------------------------------------------------------------------------------
# =========== test 12.3.2.1 PMAs: Memory Access Size, Type protection test ===========
# Tests memory load, store, and execute permissions based on table 12.3 in the *** riscv book, copied below
# Tests memory load, store, and execute permissions
# | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic |
# | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO |