Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

VCD support in all simulators

Browse Source
This commit is contained in:
Jordan Carlin 2024-12-02 13:52:44 -08:00
parent d5159d35a2
commit 783b81f8b8
No known key found for this signature in database
2 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
bin/wsim
View File

@ -78,7 +78,7 @@ def elfFileCheck(args):
def prepSim(args, ElfFile):
flags = ""
if args.vcd:
args.args += " -DMAKEVCD=1"
args.params += " MAKE_VCD=1 "
if args.rvvi:
args.params += " RVVI_SYNTH_SUPPORTED=1 "
if args.tb == "testbench_fp":

9
testbench/testbench.sv
View File

@ -44,6 +44,7 @@ module testbench;
parameter I_CACHE_ADDR_LOGGER=0;
parameter D_CACHE_ADDR_LOGGER=0;
parameter RVVI_SYNTH_SUPPORTED=0;
parameter MAKE_VCD=0;
`ifdef USE_IMPERAS_DV
import idvPkg::*;
@ -230,10 +231,10 @@ module testbench;
end
$finish;
end
`ifdef MAKEVCD
$dumpfile("testbench.vcd");
$dumpvars;
`endif
if (MAKE_VCD) begin
$dumpfile("testbench.vcd");
$dumpvars;
end
end // initial begin
// Model the testbench as an fsm.