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Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates

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Jordan Carlin 2024-08-25 12:14:25 -07:00
commit f0c5d6e4e7
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91 changed files with 1064 additions and 2664 deletions
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39
Makefile
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@ -4,45 +4,36 @@
SIM = ${WALLY}/sim
all:
make riscof
make zsbl
make testfloat
# make verify
make coverage
# make benchmarks
.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage clean
all: riscof testfloat combined_IF_vectors zsbl coverage # benchmarks
# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
riscof:
make -C sim
$(MAKE) -C sim
testfloat:
cd ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC; make
cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make
cd ${WALLY}/tests/fp; ./create_all_vectors.sh
$(MAKE) -C ${WALLY}/tests/fp vectors
combined_IF_vectors: testfloat riscof
$(MAKE) -C ${WALLY}/tests/fp combined_IF_vectors
zsbl:
$(MAKE) -C ${WALLY}/fpga/zsbl
verify:
cd ${SIM}; ./regression-wally
cd ${SIM}/sim; ./sim-testfloat-batch all
make imperasdv
benchmarks:
make coremark
make embench
$(MAKE) coremark
$(MAKE) embench
coremark:
cd ${WALLY}/benchmarks/coremark; make; make run
cd ${WALLY}/benchmarks/coremark; $(MAKE); $(MAKE) run
embench:
cd ${WALLY}/benchmarks/embench; make; make run
cd ${WALLY}/benchmarks/embench; $(MAKE); $(MAKE) run
coverage:
make -C tests/coverage
$(MAKE) -C tests/coverage
clean:
make clean -C sim
$(MAKE) clean -C sim
$(MAKE) clean -C ${WALLY}/tests/fp

BIN
addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
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Binary file not shown.

2
addins/cvw-arch-verif

@ -1 +1 @@
Subproject commit 2a4f56ec97db7cdd6fd13fb928122d408fefbf1e
Subproject commit 9d54f3f8e902bb85db74305993d2fc03796b57bc

2
bin/extractFunctionRadix.sh
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@ -3,7 +3,7 @@
######################
## extractFunctionRadix.sh
##
## Written: Ross Thompson
## Written: Rose Thompson
## email: ross1728@gmail.com
## Created: March 1, 2021
## Modified: March 10, 2021

2
bin/wally-tool-chain-install.sh
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@ -2,7 +2,7 @@
###########################################
## Tool chain install script.
##
## Written: Ross Thompson ross1728@gmail.com
## Written: Rose Thompson ross1728@gmail.com
## Created: 18 January 2023
## Modified: 22 January 2023
## Modified: 23 March 2023

2
fpga/comport.setup
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@ -1,3 +1,3 @@
sudo chown ross:ross /dev/ttyUSB1
sudo chown rose:rose /dev/ttyUSB1
stty -F /dev/ttyUSB1 57600 cs8 -cstopb -parenb
cat /dev/ttyUSB1

197
fpga/constraints/constraints-ArtyA7.xdc
View File

@ -7,34 +7,34 @@
create_generated_clock -name SPISDCClock -source [get_pins clk_out3_xlnx_mmcm] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK]
##### clock #####
set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}]
set_property PACKAGE_PIN E3 [get_ports default_100mhz_clk]
set_property IOSTANDARD LVCMOS33 [get_ports default_100mhz_clk]
##### RVVI Ethernet ####
# taken from https://github.com/alexforencich/verilog-ethernet/blob/master/example/Arty/fpga/fpga.xdc
set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv]
set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er]
set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk]
set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}]
set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}]
set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}]
set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}]
set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en]
set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col]
set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs]
set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk]
set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv]
set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er]
set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk]
set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}]
set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}]
set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}]
set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}]
set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en]
set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col]
set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs]
set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk]
set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk]
create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk]
set_false_path -to [get_ports {phy_ref_clk phy_reset_n}]
set_output_delay 0 [get_ports {phy_ref_clk phy_reset_n}]
set_output_delay 0.000 [get_ports {phy_ref_clk phy_reset_n}]
##### GPI ####
set_property PACKAGE_PIN A8 [get_ports {GPI[0]}]
@ -87,16 +87,16 @@ set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [ge
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn]
set_max_delay -from [get_ports resetn] 20.000
set_false_path -from [get_ports resetn]
set_property PACKAGE_PIN C2 [get_ports {resetn}]
set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
set_property PACKAGE_PIN C2 [get_ports resetn]
set_property IOSTANDARD LVCMOS33 [get_ports resetn]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset]
set_max_delay -from [get_ports south_reset] 20.000
set_false_path -from [get_ports south_reset]
set_property PACKAGE_PIN D9 [get_ports {south_reset}]
set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
set_property PACKAGE_PIN D9 [get_ports south_reset]
set_property IOSTANDARD LVCMOS33 [get_ports south_reset]
@ -125,19 +125,31 @@ set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
#set_property PULLUP true [get_ports {SDCCD}]
# SDCDat[3]
set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCS}]
set_property PACKAGE_PIN D4 [get_ports SDCCS]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCS]
set_property PULLTYPE PULLUP [get_ports SDCCS]
# set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}]
# set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}]
# SDCDat[0]
set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCIn}]
set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}]
set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}]
set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}]
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCWP}]
set_property PACKAGE_PIN F4 [get_ports SDCIn]
set_property IOSTANDARD LVCMOS33 [get_ports SDCIn]
set_property PULLTYPE PULLUP [get_ports SDCIn]
set_property PACKAGE_PIN F3 [get_ports SDCCLK]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
set_property PULLTYPE PULLUP [get_ports SDCCLK]
set_property PACKAGE_PIN D3 [get_ports SDCCmd]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCmd]
set_property PULLTYPE PULLUP [get_ports SDCCmd]
set_property PACKAGE_PIN H2 [get_ports SDCCD]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCD]
set_property PULLTYPE PULLUP [get_ports SDCCD]
set_property PACKAGE_PIN G2 [get_ports SDCWP]
set_property IOSTANDARD LVCMOS33 [get_ports SDCWP]
set_property PULLTYPE PULLUP [get_ports SDCWP]
set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
@ -158,54 +170,54 @@ set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc
# ddr3
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]
set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]
set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n
set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n
set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n
set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n
set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]
set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]
set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]]
set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}]
set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
@ -257,3 +269,28 @@ set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]]
set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
create_clock -period 40.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 20.000}
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin]
create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000}
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout]
#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -min -add_delay 0.000 [get_ports ddr3_reset_n]
#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -max -add_delay 80.000 [get_ports ddr3_reset_n]

80
fpga/constraints/constraints-vcu108.xdc
View File

@ -3,21 +3,22 @@
# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
# create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
create_generated_clock -name CLKDiv64_Gen -source [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q]
# create_generated_clock -name CLKDiv64_Gen -source [get_pins #wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
#create_generated_clock -name CLKDiv64_Gen -source [get_pins ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q]
create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK]
##### GPI ####
set_property PACKAGE_PIN E34 [get_ports {GPI[0]}]
set_property PACKAGE_PIN M22 [get_ports {GPI[1]}]
set_property PACKAGE_PIN AW27 [get_ports {GPI[2]}]
set_property PACKAGE_PIN A10 [get_ports {GPI[3]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}]
#set_property PACKAGE_PIN A10 [get_ports {GPI[3]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[2]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
set_max_delay -from [get_ports {GPI[*]}] 10.000n
set_max_delay -from [get_ports {GPI[*]}] 10.000
##### GPO ####
set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}]
@ -58,7 +59,7 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_port
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
set_max_delay -from [get_ports reset] 15.000
set_false_path -from [get_ports reset]
set_property PACKAGE_PIN E34 [get_ports {reset}]
set_property PACKAGE_PIN A10 [get_ports {reset}]
set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
@ -69,15 +70,6 @@ set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
##### calib #####
set_property PACKAGE_PIN BA37 [get_ports calib]
set_property IOSTANDARD LVCMOS12 [get_ports calib]
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
##### ahblite_resetn #####
set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}]
set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
@ -94,44 +86,34 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port
##### SD Card I/O #####
# set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}]
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}]
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}]
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}]
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}]
# set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}]
# set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}]
# set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}]
# set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
# set_property PACKAGE_PIN BB16 [get_ports SDCCLK]
# set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}]
# set_property PULLUP true [get_ports {SDCDat[3]}]
# set_property PULLUP true [get_ports {SDCDat[2]}]
# set_property PULLUP true [get_ports {SDCDat[1]}]
# set_property PULLUP true [get_ports {SDCDat[0]}]
# set_property PULLUP true [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK]
set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[3]}]
set_property -dict {PACKAGE_PIN BF7 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[2]}]
set_property -dict {PACKAGE_PIN BC13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[1]}]
set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[0]}]
set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}]
set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCIn}]
set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}]
set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}]
set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK]
set_property PACKAGE_PIN AW12 [get_ports SDCCD]
set_property IOSTANDARD LVCMOS18 [get_ports SDCCD]
set_property PULLTYPE PULLUP [get_ports SDCCD]
set_property PACKAGE_PIN BC16 [get_ports SDCWP]
set_property IOSTANDARD LVCMOS18 [get_ports SDCWP]
set_property PULLTYPE PULLUP [get_ports SDCWP]
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
#set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
#set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
#set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
@ -264,8 +246,8 @@ set_property PACKAGE_PIN D27 [get_ports {c0_ddr4_dm_dbi_n[7]}]
set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
#set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
#set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]

5
fpga/constraints/marked_debug.txt
View File

@ -3,8 +3,5 @@ wally/wallypipelinedcore.sv: logic TrapM
wally/wallypipelinedcore.sv: logic InstrValidM
wally/wallypipelinedcore.sv: logic InstrM
lsu/lsu.sv: logic IEUAdrM
lsu/lsu.sv: logic PAdrM
lsu/lsu.sv: logic ReadDataM
lsu/lsu.sv: logic WriteDataM
lsu/lsu.sv: logic MemRWM
privileged/csrc.sv: logic HPMCOUNTER_REGW
mmu/hptw.sv: logic SATP_REGW

10
fpga/constraints/marked_debug_rvvi.txt Normal file
View File

@ -0,0 +1,10 @@
wally/wallypipelinedcore.sv: logic PCM
wally/wallypipelinedcore.sv: logic TrapM
wally/wallypipelinedcore.sv: logic InstrValidM
wally/wallypipelinedcore.sv: logic InstrM
lsu/lsu.sv: logic IEUAdrM
lsu/lsu.sv: logic PAdrM
lsu/lsu.sv: logic ReadDataM
lsu/lsu.sv: logic WriteDataM
lsu/lsu.sv: logic MemRWM
privileged/csrc.sv: logic HPMCOUNTER_REGW

2
fpga/constraints/vcu-small-debug.xdc
View File

@ -1,6 +1,6 @@
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]

20
fpga/generator/Makefile
View File

@ -27,19 +27,15 @@ FPGA_VCU: PreProcessFiles IP_VCU
# Generate IP Blocks
.PHONY: IP_Arty IP_VCU
IP_VCU: $(dst)/xlnx_proc_sys_reset.log \
IP_VCU: $(dst)/sysrst.log \
MEM_VCU \
$(dst)/xlnx_axi_clock_converter.log \
$(dst)/xlnx_ahblite_axi_bridge.log \
$(dst)/xlnx_axi_crossbar.log \
$(dst)/xlnx_axi_dwidth_conv_32to64.log \
$(dst)/xlnx_axi_dwidth_conv_64to32.log \
$(dst)/xlnx_axi_prtcl_conv.log
IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
$(dst)/clkconverter.log \
$(dst)/ahbaxibridge.log
IP_Arty: $(dst)/sysrst.log \
MEM_Arty \
$(dst)/xlnx_mmcm.log \
$(dst)/xlnx_axi_clock_converter.log \
$(dst)/xlnx_ahblite_axi_bridge.log
$(dst)/clkconverter.log \
$(dst)/ahbaxibridge.log
#$(dst)/xlnx_axi_crossbar.log \
#$(dst)/xlnx_axi_dwidth_conv_32to64.log \
#$(dst)/xlnx_axi_dwidth_conv_64to32.log \
@ -48,9 +44,9 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
# Generate Memory IP Blocks
.PHONY: MEM_VCU MEM_Arty
MEM_VCU:
$(MAKE) $(dst)/xlnx_ddr4-$(board).log
$(MAKE) $(dst)/ddr4-$(board).log
MEM_Arty:
$(MAKE) $(dst)/xlnx_ddr3-$(board).log
$(MAKE) $(dst)/ddr3-$(board).log
# Copy files and make necessary modifications
.PHONY: PreProcessFiles

10
fpga/generator/xlnx_ahblite_axi_bridge.tcl → fpga/generator/ahbaxibridge.tcl
View File

@ -2,15 +2,7 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
# vcu118 board
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_ahblite_axi_bridge
set ipName ahbaxibridge
create_project $ipName . -force -part $partNumber
if {$boardName!="ArtyA7"} {

2
fpga/generator/xlnx_axi_clock_converter.tcl → fpga/generator/clkconverter.tcl
View File

@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
set ipName xlnx_axi_clock_converter
set ipName clkconverter
create_project $ipName . -force -part $partNumber
if {$boardName!="ArtyA7"} {

2
fpga/generator/xlnx_ddr3-ArtyA7.tcl → fpga/generator/ddr3-ArtyA7.tcl
View File

@ -2,7 +2,7 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set ipName xlnx_ddr3
set ipName ddr3
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]

18
fpga/generator/xlnx_ddr4-vcu108.tcl → fpga/generator/ddr4-vcu108.tcl
View File

@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
set ipName xlnx_ddr4
set ipName ddr4
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
@ -15,12 +15,12 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.No_Controller {1} \
CONFIG.Phy_Only {Complete_Memory_Controller} \
CONFIG.C0.DDR4_PhyClockRatio {4:1} \
CONFIG.C0.DDR4_TimePeriod {1200} \
CONFIG.C0.DDR4_TimePeriod {833} \
CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
CONFIG.C0.DDR4_BurstLength {8} \
CONFIG.C0.DDR4_BurstType {Sequential} \
CONFIG.C0.DDR4_CasLatency {13} \
CONFIG.C0.DDR4_CasWriteLatency {10} \
CONFIG.C0.DDR4_CasLatency {16} \
CONFIG.C0.DDR4_CasWriteLatency {12} \
CONFIG.C0.DDR4_Slot {Single} \
CONFIG.C0.DDR4_MemoryVoltage {1.2V} \
CONFIG.C0.DDR4_DataWidth {64} \
@ -36,14 +36,11 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_AxiIDWidth {4} \
CONFIG.C0.DDR4_AxiAddressWidth {31} \
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \
CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \
CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \
@ -106,7 +103,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_CustomParts {no_file_loaded} \
CONFIG.C0.DDR4_EN_PARITY {false} \
CONFIG.C0.DDR4_Enable_LVAUX {false} \
CONFIG.C0.DDR4_InputClockPeriod {3359} \
CONFIG.C0.DDR4_InputClockPeriod {3332} \
CONFIG.C0.DDR4_LR_SKEW_0 {0} \
CONFIG.C0.DDR4_LR_SKEW_1 {0} \
CONFIG.C0.DDR4_MemoryName {MainMemory} \
@ -115,6 +112,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_ODT_SKEW_2 {0} \
CONFIG.C0.DDR4_ODT_SKEW_3 {0} \
CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \
CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \
CONFIG.C0.DDR4_PAR_SKEW {0} \
CONFIG.C0.DDR4_Specify_MandD {false} \
CONFIG.C0.DDR4_TREFI {0} \

2
fpga/generator/xlnx_ddr4-vcu118.tcl → fpga/generator/ddr4-vcu118.tcl
View File

@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
set ipName xlnx_ddr4
set ipName ddr4
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]

4
fpga/generator/xlnx_mmcm.tcl → fpga/generator/mmcm.tcl
View File

@ -1,7 +1,7 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set ipName xlnx_mmcm
set ipName mmcm
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \
CONFIG.CLKIN1_JITTER_PS {10.0} \
] [get_ips $ipName]

2
fpga/generator/xlnx_proc_sys_reset.tcl → fpga/generator/sysrst.tcl
View File

@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
set ipName xlnx_proc_sys_reset
set ipName sysrst
create_project $ipName . -force -part $partNumber
if {$boardName!="ArtyA7"} {

42
fpga/generator/wally.tcl
View File

@ -5,6 +5,11 @@ set boardName $::env(XILINX_BOARD)
set boardSubName [lindex [split ${boardName} :] 1]
set board $::env(board)
#set partNumber xc7a100tcsg324-1
#set boardName digilentinc.com:arty-a7-100:part0:1.1
#set boardSubName arty-a7-100
#set board ArtyA7
set ipName WallyFPGA
create_project $ipName . -force -part $partNumber
@ -23,20 +28,15 @@ if {$board=="ArtyA7"} {
}
# read in ip
read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci
read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci
read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
# Added crossbar - Jacob Pease <2023-01-12 Thu>
#read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci
#read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci
#read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci
#read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci
import_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci
import_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci
import_ip IP/clkconverter.srcs/sources_1/ip/clkconverter/clkconverter.xci
if {$board=="ArtyA7"} {
read_ip IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/xlnx_ddr3.xci
read_ip IP/xlnx_mmcm.srcs/sources_1/ip/xlnx_mmcm/xlnx_mmcm.xci
import_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci
import_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci
} else {
read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
import_ip IP/ddr4.srcs/sources_1/ip/ddr4/ddr4.xci
}
# read in all other rtl
@ -46,13 +46,6 @@ read_verilog [glob -type f ../../addins/ahbsdc/sdc/*.v]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset]
if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
} else {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
}
# define top level
set_property top fpgaTop [current_fileset]
@ -62,6 +55,14 @@ update_compile_order -fileset sources_1
exec mkdir -p reports/
exec rm -rf reports/*
if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
} else {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
}
report_compile_order -constraints > reports/compile_order.rpt
# this is elaboration not synthesis.
@ -89,10 +90,11 @@ report_clock_interaction -file re
write_verilog -force -mode funcsim sim/syn-funcsim.v
if {$board=="ArtyA7"} {
source ../constraints/small-debug.xdc
#source ../constraints/small-debug.xdc
#source ../constraints/small-debug-rvvi.xdc
} else {
source ../constraints/vcu-small-debug.xdc
#source ../constraints/vcu-small-debug.xdc
source ../constraints/small-debug.xdc
}

32
fpga/generator/xlnx_axi_crossbar.tcl
View File

@ -1,32 +0,0 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
# vcu118 board
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_axi_crossbar
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
set_property -dict [list CONFIG.NUM_SI {2} \
CONFIG.DATA_WIDTH {64} \
CONFIG.ID_WIDTH {4} \
CONFIG.M01_S01_READ_CONNECTIVITY {0} \
CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \
CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \
CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \
CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

25
fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl
View File

@ -1,25 +0,0 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
# vcu118 board
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_axi_dwidth_conv_32to64
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_32to64}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

27
fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl
View File

@ -1,27 +0,0 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
# vcu118 board
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_axi_dwidth_conv_64to32
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_64to32} \
CONFIG.SI_DATA_WIDTH {64} \
CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

25
fpga/generator/xlnx_axi_dwidth_converter.tcl
View File

@ -1,25 +0,0 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
# vcu118 board
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_axi_dwidth_converter
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
set_property -dict [list CONFIG.Component_Name {axi_dwidth_converter}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

23
fpga/generator/xlnx_axi_prtcl_conv.tcl
View File

@ -1,23 +0,0 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
# vcu118 board
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_axi_prtcl_conv
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

2
fpga/generator/xlnx_ddr4.tcl
View File

@ -5,7 +5,7 @@ set partNumber xcvu095-ffva2104-2-e
set boardName xilinx.com:vcu108:part0:1.2
set ipName xlnx_ddr4
set ipName ddr4
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]

1018
fpga/src/fpgaTop.sv
View File

File diff suppressed because it is too large Load Diff

314
fpga/src/fpgaTopArtyA7.sv
View File

@ -29,183 +29,183 @@
import cvw::*;
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
(input default_100mhz_clk,
(* mark_debug = "true" *) input resetn,
input south_reset,
(input logic default_100mhz_clk,
input logic resetn,
input logic south_reset,
// GPIO signals
input [3:0] GPI,
output [4:0] GPO,
input logic [3:0] GPI,
output logic [4:0] GPO,
// UART Signals
input UARTSin,
output UARTSout,
input logic UARTSin,
output logic UARTSout,
// SDC Signals connecting to an SPI peripheral
input SDCIn,
output SDCCLK,
output SDCCmd,
output SDCCS,
input SDCCD,
input SDCWP,
input logic SDCIn,
output logic SDCCLK,
output logic SDCCmd,
output logic SDCCS,
input logic SDCCD,
input logic SDCWP,
/*
* Ethernet: 100BASE-T MII
*/
output phy_ref_clk,
input phy_rx_clk,
input [3:0] phy_rxd,
input phy_rx_dv,
input phy_rx_er,
input phy_tx_clk,
output [3:0] phy_txd,
output phy_tx_en,
input phy_col, // nc
input phy_crs, // nc
output phy_reset_n,
output logic phy_ref_clk,
input logic phy_rx_clk,
input logic [3:0] phy_rxd,
input logic phy_rx_dv,
input logic phy_rx_er,
input logic phy_tx_clk,
output logic [3:0] phy_txd,
output logic phy_tx_en,
input logic phy_col, // nc
input logic phy_crs, // nc
output logic phy_reset_n,
inout [15:0] ddr3_dq,
inout [1:0] ddr3_dqs_n,
inout [1:0] ddr3_dqs_p,
output [13:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [0:0] ddr3_ck_p,
output [0:0] ddr3_ck_n,
output [0:0] ddr3_cke,
output [0:0] ddr3_cs_n,
output [1:0] ddr3_dm,
output [0:0] ddr3_odt
inout logic [15:0] ddr3_dq,
inout logic [1:0] ddr3_dqs_n,
inout logic [1:0] ddr3_dqs_p,
output logic [13:0] ddr3_addr,
output logic [2:0] ddr3_ba,
output logic ddr3_ras_n,
output logic ddr3_cas_n,
output logic ddr3_we_n,
output logic ddr3_reset_n,
output logic [0:0] ddr3_ck_p,
output logic [0:0] ddr3_ck_n,
output logic [0:0] ddr3_cke,
output logic [0:0] ddr3_cs_n,
output logic [1:0] ddr3_dm,
output logic [0:0] ddr3_odt
);
// MMCM Signals
wire CPUCLK;
wire c0_ddr4_ui_clk_sync_rst;
wire bus_struct_reset;
wire peripheral_reset;
wire interconnect_aresetn;
wire peripheral_aresetn;
wire mb_reset;
logic CPUCLK;
logic c0_ddr4_ui_clk_sync_rst;
logic bus_struct_reset;
logic peripheral_reset;
logic interconnect_aresetn;
logic peripheral_aresetn;
logic mb_reset;
// AHB Signals from Wally
wire HCLKOpen;
wire HRESETnOpen;
wire [63:0] HRDATAEXT;
wire HREADYEXT;
wire HRESPEXT;
wire HSELEXT;
wire [55:0] HADDR;
wire [63:0] HWDATA;
wire [64/8-1:0] HWSTRB;
wire HWRITE;
wire [2:0] HSIZE;
wire [2:0] HBURST;
wire [1:0] HTRANS;
wire HREADY;
wire [3:0] HPROT;
wire HMASTLOCK;
logic HCLKOpen;
logic HRESETnOpen;
logic [63:0] HRDATAEXT;
logic HREADYEXT;
logic HRESPEXT;
logic HSELEXT;
logic [55:0] HADDR;
logic [63:0] HWDATA;
logic [64/8-1:0] HWSTRB;
logic HWRITE;
logic [2:0] HSIZE;
logic [2:0] HBURST;
logic [1:0] HTRANS;
logic HREADY;
logic [3:0] HPROT;
logic HMASTLOCK;
// GPIO Signals
wire [31:0] GPIOIN, GPIOOUT, GPIOEN;
logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
// AHB to AXI Bridge Signals
wire [3:0] m_axi_awid;
wire [7:0] m_axi_awlen;
wire [2:0] m_axi_awsize;
wire [1:0] m_axi_awburst;
wire [3:0] m_axi_awcache;
wire [31:0] m_axi_awaddr;
wire [2:0] m_axi_awprot;
wire m_axi_awvalid;
wire m_axi_awready;
wire m_axi_awlock;
wire [63:0] m_axi_wdata;
wire [7:0] m_axi_wstrb;
wire m_axi_wlast;
wire m_axi_wvalid;
wire m_axi_wready;
wire [3:0] m_axi_bid;
wire [1:0] m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_bready;
wire [3:0] m_axi_arid;
wire [7:0] m_axi_arlen;
wire [2:0] m_axi_arsize;
wire [1:0] m_axi_arburst;
wire [2:0] m_axi_arprot;
wire [3:0] m_axi_arcache;
wire m_axi_arvalid;
wire [31:0] m_axi_araddr;
wire m_axi_arlock;
wire m_axi_arready;
wire [3:0] m_axi_rid;
wire [63:0] m_axi_rdata;
wire [1:0] m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_rlast;
wire m_axi_rready;
logic [3:0] m_axi_awid;
logic [7:0] m_axi_awlen;
logic [2:0] m_axi_awsize;
logic [1:0] m_axi_awburst;
logic [3:0] m_axi_awcache;
logic [31:0] m_axi_awaddr;
logic [2:0] m_axi_awprot;
logic m_axi_awvalid;
logic m_axi_awready;
logic m_axi_awlock;
logic [63:0] m_axi_wdata;
logic [7:0] m_axi_wstrb;
logic m_axi_wlast;
logic m_axi_wvalid;
logic m_axi_wready;
logic [3:0] m_axi_bid;
logic [1:0] m_axi_bresp;
logic m_axi_bvalid;
logic m_axi_bready;
logic [3:0] m_axi_arid;
logic [7:0] m_axi_arlen;
logic [2:0] m_axi_arsize;
logic [1:0] m_axi_arburst;
logic [2:0] m_axi_arprot;
logic [3:0] m_axi_arcache;
logic m_axi_arvalid;
logic [31:0] m_axi_araddr;
logic m_axi_arlock;
logic m_axi_arready;
logic [3:0] m_axi_rid;
logic [63:0] m_axi_rdata;
logic [1:0] m_axi_rresp;
logic m_axi_rvalid;
logic m_axi_rlast;
logic m_axi_rready;
// AXI Signals going out of Clock Converter
wire [3:0] BUS_axi_arregion;
wire [3:0] BUS_axi_arqos;
wire [3:0] BUS_axi_awregion;
wire [3:0] BUS_axi_awqos;
wire [3:0] BUS_axi_awid;
wire [7:0] BUS_axi_awlen;
wire [2:0] BUS_axi_awsize;
wire [1:0] BUS_axi_awburst;
wire [3:0] BUS_axi_awcache;
wire [31:0] BUS_axi_awaddr;
wire [2:0] BUS_axi_awprot;
wire BUS_axi_awvalid;
wire BUS_axi_awready;
wire BUS_axi_awlock;
wire [63:0] BUS_axi_wdata;
wire [7:0] BUS_axi_wstrb;
wire BUS_axi_wlast;
wire BUS_axi_wvalid;
wire BUS_axi_wready;
wire [3:0] BUS_axi_bid;
wire [1:0] BUS_axi_bresp;
wire BUS_axi_bvalid;
wire BUS_axi_bready;
wire [3:0] BUS_axi_arid;
wire [7:0] BUS_axi_arlen;
wire [2:0] BUS_axi_arsize;
wire [1:0] BUS_axi_arburst;
wire [2:0] BUS_axi_arprot;
wire [3:0] BUS_axi_arcache;
wire BUS_axi_arvalid;
wire [31:0] BUS_axi_araddr;
wire BUS_axi_arlock;
wire BUS_axi_arready;
wire [3:0] BUS_axi_rid;
wire [63:0] BUS_axi_rdata;
wire [1:0] BUS_axi_rresp;
wire BUS_axi_rvalid;
wire BUS_axi_rlast;
wire BUS_axi_rready;
logic [3:0] BUS_axi_arregion;
logic [3:0] BUS_axi_arqos;
logic [3:0] BUS_axi_awregion;
logic [3:0] BUS_axi_awqos;
logic [3:0] BUS_axi_awid;
logic [7:0] BUS_axi_awlen;
logic [2:0] BUS_axi_awsize;
logic [1:0] BUS_axi_awburst;
logic [3:0] BUS_axi_awcache;
logic [31:0] BUS_axi_awaddr;
logic [2:0] BUS_axi_awprot;
logic BUS_axi_awvalid;
logic BUS_axi_awready;
logic BUS_axi_awlock;
logic [63:0] BUS_axi_wdata;
logic [7:0] BUS_axi_wstrb;
logic BUS_axi_wlast;
logic BUS_axi_wvalid;
logic BUS_axi_wready;
logic [3:0] BUS_axi_bid;
logic [1:0] BUS_axi_bresp;
logic BUS_axi_bvalid;
logic BUS_axi_bready;
logic [3:0] BUS_axi_arid;
logic [7:0] BUS_axi_arlen;
logic [2:0] BUS_axi_arsize;
logic [1:0] BUS_axi_arburst;
logic [2:0] BUS_axi_arprot;
logic [3:0] BUS_axi_arcache;
logic BUS_axi_arvalid;
logic [31:0] BUS_axi_araddr;
logic BUS_axi_arlock;
logic BUS_axi_arready;
logic [3:0] BUS_axi_rid;
logic [63:0] BUS_axi_rdata;
logic [1:0] BUS_axi_rresp;
logic BUS_axi_rvalid;
logic BUS_axi_rlast;
logic BUS_axi_rready;
wire BUSCLK;
wire sdio_reset_open;
logic BUSCLK;
logic sdio_reset_open;
wire c0_init_calib_complete;
wire dbg_clk;
wire [511 : 0] dbg_bus;
wire ui_clk_sync_rst;
logic c0_init_calib_complete;
logic dbg_clk;
logic [511 : 0] dbg_bus;
logic ui_clk_sync_rst;
wire CLK208;
wire clk167;
wire clk200;
logic CLK208;
logic clk167;
logic clk200;
wire app_sr_active;
wire app_ref_ack;
wire app_zq_ack;
wire mmcm_locked;
wire [11:0] device_temp;
wire mmcm1_locked;
logic app_sr_active;
logic app_ref_ack;
logic app_zq_ack;
logic mmcm_locked;
logic [11:0] device_temp;
logic mmcm1_locked;
(* mark_debug = "true" *) logic RVVIStall;
@ -225,7 +225,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
// 2. a second clock which is 200 MHz
// Wally requires a slower clock. At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz.
// the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot.
xlnx_mmcm xln_mmcm(.clk_out1(clk167),
mmcm mmcm(.clk_out1(clk167),
.clk_out2(clk200),
.clk_out3(CPUCLK),
.clk_out4(phy_ref_clk),
@ -236,7 +236,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
// reset controller XILINX IP
xlnx_proc_sys_reset xlnx_proc_sys_reset_0
sysrst sysrst
(.slowest_sync_clk(CPUCLK),
.ext_reset_in(1'b0),
.aux_reset_in(south_reset),
@ -262,7 +262,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
// ahb lite to axi bridge
xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0
ahbaxibridge ahbaxibridge
(.s_ahb_hclk(CPUCLK),
.s_ahb_hresetn(peripheral_aresetn),
.s_ahb_hsel(HSELEXT),
@ -314,7 +314,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
.m_axi_rready(m_axi_rready));
// AXI Clock Converter
xlnx_axi_clock_converter xlnx_axi_clock_converter_0
clkconverter clkconverter
(.s_axi_aclk(CPUCLK),
.s_axi_aresetn(peripheral_aresetn),
.s_axi_awid(m_axi_awid),
@ -400,7 +400,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
.m_axi_rready(BUS_axi_rready));
// DDR3 Controller
xlnx_ddr3 xlnx_ddr3_c0
ddr3 ddr3
(
// ddr3 I/O
.ddr3_dq(ddr3_dq),

2
fpga/src/wallypipelinedsocwrapper.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// wallypipelinedsocwrapper.sv
//
// Written: Ross Thompson ross1728@gmail.com 16 June 2023
// Written: Rose Thompson ross1728@gmail.com 16 June 2023
// Modified:
//
// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog,

61
fpga/zsbl/boot.c
View File

@ -37,12 +37,29 @@
#include "riscv.h"
#include "fail.h"
// Maximum SD card clock frequency is either 20MHz or half of the
// system clock
/*
PSEUDOCODE:
transmit 8 dummy bytes
wait for receive fifo to get a byte.
- as soon as a byte is in the receive fifo
- process the byte and increment a byte counter.
when 8 bytes are transferred
*/
int disk_read(BYTE * buf, LBA_t sector, UINT count) {
uint64_t r;
UINT i;
UINT i, j;
volatile uint8_t *p = buf;
UINT modulus = count/50;
// Quarter of the Systemclock, divided by the number of bits in a block
// equals the number of blocks per second transferred.
UINT modulus = SDCCLOCK/(8*512);
uint8_t crc = 0;
crc = crc7(crc, 0x40 | SD_CMD_READ_BLOCK_MULTIPLE);
@ -72,22 +89,30 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
// Wait for data token
while((r = spi_dummy()) != SD_DATA_TOKEN);
// println_with_byte("Received data token: 0x", r & 0xff);
// println_with_dec("Block ", i);
// Read block into memory.
/* for (int j = 0; j < 64; j++) { */
/* *buf = sd_read64(&crc); */
/* println_with_addr("0x", *buf); */
/* buf = buf + 64; */
/* } */
crc = 0;
n = 512;
/* n = 512; */
/* do { */
/* uint8_t x = spi_dummy(); */
/* *p++ = x; */
/* crc = crc16(crc, x); */
/* } while (--n > 0); */
n = 512/8;
do {
uint8_t x = spi_dummy();
*p++ = x;
crc = crc16(crc, x);
} while (--n > 0);
// Send 8 dummy bytes (fifo should be empty)
for (j = 0; j < 8; j++) {
spi_sendbyte(0xff);
}
// Reset counter. Process bytes AS THEY COME IN.
for (j = 0; j < 8; j++) {
while (!(read_reg(SPI_IP) & 2)) {}
uint8_t x = spi_readbyte();
*p++ = x;
crc = crc16(crc, x);
}
} while(--n > 0);
// Read CRC16 and check
crc_exp = ((uint16_t)spi_dummy() << 8);
@ -116,8 +141,6 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
print_uart_dec(count);
print_uart("/");
print_uart_dec(count);
// write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_AUTO);
//spi_txrx(0xff);
print_uart("\r\n");
return 0;
}
@ -130,7 +153,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
int ret = 0;
// Initialize UART for messages
init_uart(20000000, 115200);
init_uart(SYSTEMCLOCK, 115200);
// Print the wally banner
print_uart(BANNER);
@ -140,7 +163,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
/* print_uart("\r\n"); */
// Intialize the SD card
init_sd(SYSTEMCLOCK, 5000000);
init_sd(SYSTEMCLOCK, SDCCLOCK);
ret = gpt_load_partitions();
}

9
fpga/zsbl/boot.h
View File

@ -63,5 +63,14 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count);
#define SYSTEMCLOCK 20000000
// TODO: This line needs to change back to 20MHz when we fix the
// timing problems.
#define MAXSDCCLOCK 5000000
// Maximum SDC speed is either the system clock divided by 2 (because
// of the SPI peripheral clock division) or the maximum speed an SD
// card can be pushed to.
#define SDCCLOCK (SYSTEMCLOCK/2 > MAXSDCCLOCK ? MAXSDCCLOCK : SYSTEMCLOCK/2)
#endif // WALLYBOOT

8
linux/devicetree/wally-artya7.dts
View File

@ -21,8 +21,8 @@
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
clock-frequency = <0x1312D00>;
timebase-frequency = <0x1312D00>;
clock-frequency = <0x17D7840>;
timebase-frequency = <0x17D7840>;
cpu@0 {
phandle = <0x01>;
@ -54,7 +54,7 @@
refclk: refclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0x1312D00>;
clock-frequency = <0x17D7840>;
clock-output-names = "xtal";
};
@ -73,7 +73,7 @@
uart@10000000 {
interrupts = <0x0a>;
interrupt-parent = <0x03>;
clock-frequency = <0x1312D00>;
clock-frequency = <0x17D7840>;
reg = <0x00 0x10000000 0x00 0x100>;
compatible = "ns16550a";
};

58
linux/devicetree/wally-vcu108.dts
View File

@ -9,7 +9,7 @@
chosen {
linux,initrd-end = <0x85c43a00>;
linux,initrd-start = <0x84200000>;
bootargs = "console=ttyS0,115200 root=/dev/vda ro";
bootargs = "root=/dev/vda ro console=ttyS0,115200 loglevel=7";
stdout-path = "/soc/uart@10000000";
};
@ -21,8 +21,8 @@
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
clock-frequency = <0x14FB180>;
timebase-frequency = <0x14FB180>;
clock-frequency = <0x2FAF080>;
timebase-frequency = <0x2FAF080>;
cpu@0 {
phandle = <0x01>;
@ -31,6 +31,9 @@
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
riscv,cbom-block-size = <64>;
mmu-type = "riscv,sv48";
interrupt-controller {
@ -48,10 +51,29 @@
compatible = "simple-bus";
ranges;
refclk: refclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0x2FAF080>;
clock-output-names = "xtal";
};
gpio0: gpio@10060000 {
compatible = "sifive,gpio0";
interrupt-parent = <0x03>;
interrupts = <3>;
reg = <0x00 0x10060000 0x00 0x1000>;
reg-names = "control";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
uart@10000000 {
interrupts = <0x0a>;
interrupt-parent = <0x03>;
clock-frequency = <0x14FB180>;
clock-frequency = <0x2FAF080>;
reg = <0x00 0x10000000 0x00 0x100>;
compatible = "ns16550a";
};
@ -67,18 +89,24 @@
#address-cells = <0x00>;
};
mmc@13000 {
interrupts = <0x14>;
compatible = "riscv,axi-sd-card-1.0";
reg = <0x00 0x13000 0x00 0x7F>;
fifo-depth = <256>;
bus-width = <4>;
spi@13000 {
compatible = "sifive,spi0";
interrupt-parent = <0x03>;
clock = <0x14FB180>;
max-frequency = <0xA7D8C0>;
cap-sd-highspeed;
cap-mmc-highspeed;
no-sdio;
interrupts = <0x14>;
reg = <0x0 0x13000 0x0 0x1000>;
reg-names = "control";
clocks = <&refclk>;
#address-cells = <1>;
#size-cells = <0>;
mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
spi-max-frequency = <5000000>;
voltage-ranges = <3300 3300>;
disable-wp;
// gpios = <&gpio0 6 1>;
};
};
clint@2000000 {

2
linux/testvector-generation/parseGDBtoTrace.py
View File

@ -1,7 +1,7 @@
#!/usr/bin/env python3
import sys, fileinput, re
# Ross Thompson
# Rose Thompson
# July 27, 2021
# Rewrite of the linux trace parser.

12
sim/Makefile
View File

@ -30,14 +30,22 @@ QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb
# vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt
vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb
QuestaFunctCoverage: ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb
vcover merge -out ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY*.ucdb -logfile ${SIM}/questa/fcov_logs/log
QuestaFunctCoverage: ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY-COV-add.elf.ucdb
vcover merge -out ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY-COV-add.elf.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY*.ucdb -logfile ${SIM}/questa/fcov_logs/log
vcover report -details -html ${SIM}/questa/fcov_ucdb/fcov.ucdb
vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg > ${SIM}/questa/fcov/fcov.log
vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -testdetails -cvg > ${SIM}/questa/fcov/fcov.testdetails.log
vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE" > ${SIM}/questa/fcov/fcov.summary.log
grep "TOTAL COVERGROUP COVERAGE" ${SIM}/questa/fcov/fcov.log
QuestaFunctCoverageRvvi: ${WALLY}/addins/cvw-arch-verif/work/rv64gc_arch64i.ucdb
vcover merge -out ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb ${WALLY}/addins/cvw-arch-verif/work/rv64gc_arch64i.ucdb ${WALLY}/addins/cvw-arch-verif/work/rv64gc_*.ucdb -logfile ${SIM}/questa/fcovrvvi/log
vcover report -details -html ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb
vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -details -cvg > ${SIM}/questa/fcovrvvi/fcovrvvi.log
vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -testdetails -cvg > ${SIM}/questa/fcovrvvi/fcovrvvi.testdetails.log
vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE" > ${SIM}/questa/fcovrvvi/fcovrvvi.summary.log
grep "TOTAL COVERGROUP COVERAGE" ${SIM}/questa/fcovrvvi/fcovrvvi.log
imperasdv_cov:
touch ${SIM}/seed0.txt
echo "0" > ${SIM}/seed0.txt

2
sim/questa/wally.do
View File

@ -183,7 +183,7 @@ if {$DEBUG > 0} {
# because vsim will run vopt
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
vlog -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2583 -suppress 7063,2596,13286
vlog -lint +nowarnRDGN -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2244 -suppress 2282 -suppress 2583 -suppress 7063,2596,13286
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals

20
sim/questa/wave.do
View File

@ -204,7 +204,7 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
@ -657,22 +657,6 @@ add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
add wave -noupdate -expand -group testbench /testbench/DCacheFlushStart
add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFault
add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFaultDelay
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/clk
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/rvvi
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/valid
add wave -noupdate -group packetizer -color Gold /testbench/rvvi_synth/packetizer/CurrState
add wave -noupdate -group packetizer -radix unsigned /testbench/rvvi_synth/packetizer/WordCount
add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/RVVIStall
add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/rvviDelay
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWdata
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWlast
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWstrb
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWvalid
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWready
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_clk
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_txd
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_en
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_er
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {554 ns} 0} {{Cursor 4} {120089 ns} 0}
quietly wave cursor active 4
@ -690,4 +674,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {1033211 ns}
WaveRestoreZoom {0 ns} {755549 ns}

2
src/cache/cache.sv vendored
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// cache.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 7 July 2021
// Modified: 20 January 2023
//

2
src/cache/cachefsm.sv vendored
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// cachefsm.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 25 August 2021
// Modified: 20 January 2023
//

2
src/cache/subcachelineread.sv vendored
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// subcachelineread.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 4 February 2022
// Modified: 20 January 2023
//

2
src/ebu/ahbcacheinterface.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// ahbcacheinterface.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022
// Modified: 18 January 2023
//

2
src/ebu/ahbinterface.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// ahbinterface.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022
// Modified: 18 January 2023
//

2
src/ebu/buscachefsm.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// busfsm.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: December 29, 2021
// Modified: 18 January 2023
//

2
src/ebu/busfsm.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// busfsm.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: December 29, 2021
// Modified: 18 January 2023
//

2
src/ebu/controllerinput.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// controllerinput.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: August 31, 2022
// Modified: 18 January 2023
//

2
src/ebu/ebu.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// abhmulticontroller
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022
// Modified: 18 January 2023
//

2
src/ebu/ebufsmarb.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// ebufsmarb.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 23 January 2023
// Modified: 23 January 2023
//

2
src/generic/arrs.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// arrs.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Modified: November 12, 2021
//
// Purpose: resets are typically asynchronous but need to be synchronized to

2
src/ifu/bpred/RASPredictor.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// RASPredictor.sv
//
// Written: Ross Thomposn ross1728@gmail.com
// Written: Rose Thomposn ross1728@gmail.com
// Created: 15 February 2021
// Modified: 25 January 2023
//

2
src/ifu/bpred/bpred.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// bpred.sv
//
// Written: Ross Thomposn ross1728@gmail.com
// Written: Rose Thomposn ross1728@gmail.com
// Created: 12 February 2021
// Modified: 19 January 2023
//

2
src/ifu/bpred/btb.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// btb.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: February 15, 2021
// Modified: 24 January 2023
//

2
src/ifu/bpred/gshare.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// gshare.sv
//
// Written: Ross Thompson
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai)

2
src/ifu/bpred/gsharebasic.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// gsharebasic.sv
//
// Written: Ross Thompson
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.

2
src/ifu/bpred/icpred.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// icpred.sv
//
// Written: Ross Thomposn ross1728@gmail.com
// Written: Rose Thomposn ross1728@gmail.com
// Created: February 26, 2023
// Modified: February 26, 2023
//

2
src/ifu/bpred/localaheadbp.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// localaheadbp
//
// Written: Ross Thompson
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Created: 16 March 2021
//

2
src/ifu/bpred/localbpbasic.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// localbpbasic
//
// Written: Ross Thompson
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Created: 16 March 2021
//

2
src/ifu/bpred/localrepairbp.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// localrepairbp
//
// Written: Ross Thompson
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Created: 15 April 2023
//

2
src/ifu/bpred/satCounter2.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// satCounter2.sv
//
// Written: Ross Thomposn
// Written: Rose Thomposn
// Email: ross1728@gmail.com
// Created: February 13, 2021
// Modified:

2
src/ifu/bpred/twoBitPredictor.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// twoBitPredictor.sv
//
// Written: Ross Thomposn
// Written: Rose Thomposn
// Email: ross1728@gmail.com
// Created: February 14, 2021
// Modified:

2
src/ifu/irom.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// irom.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 30 January 2022
// Modified: 18 January 2023
//

2
src/ifu/spill.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// spill.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 28 January 2022
// Modified: 19 January 2023
//

2
src/lsu/atomic.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// atomic.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 31 January 2022
// Modified: 18 January 2023
//

2
src/lsu/dtim.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// dtim.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Created: 30 January 2022
// Modified: 18 January 2023
//

59
src/uncore/spi_apb.sv
View File

@ -148,8 +148,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
// APB access
assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
assign Memwrite = PWRITE & PENABLE & PSEL; // Only write in access phase
// JACOB: This shouldn't behave this way
assign PREADY = TransmitInactive; // Tie PREADY to transmission for hardware interlock
assign PREADY = Entry == SPI_TXDATA | Entry == SPI_RXDATA | Entry == SPI_IP | TransmitInactive; // Tie PREADY to transmission for hardware interlock
// Account for subword read/write circuitry
// -- Note SPI registers are 32 bits no matter what; access them with LW SW.
@ -187,12 +186,16 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
SPI_CSMODE: ChipSelectMode <= Din[1:0];
SPI_DELAY0: Delay0 <= {Din[23:16], Din[7:0]};
SPI_DELAY1: Delay1 <= {Din[23:16], Din[7:0]};
SPI_FMT: Format <= {Din[19:16], Din[2]};
SPI_TXDATA: if (~TransmitFIFOWriteFull) TransmitData[7:0] <= Din[7:0];
SPI_FMT: Format <= {Din[19:16], Din[2]};
SPI_TXMARK: TransmitWatermark <= Din[2:0];
SPI_RXMARK: ReceiveWatermark <= Din[2:0];
SPI_IE: InterruptEnable <= Din[1:0];
endcase
if (Memwrite)
case(Entry)
SPI_TXDATA: if (~TransmitFIFOWriteFull) TransmitData[7:0] <= Din[7:0];
endcase
/* verilator lint_off CASEINCOMPLETE */
// According to FU540 spec: Once interrupt is pending, it will remain set until number
@ -268,11 +271,11 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
always_ff @(posedge PCLK)
if (~PRESETn) TransmitFIFOWriteIncrement <= 1'b0;
else TransmitFIFOWriteIncrement <= (Memwrite & (Entry == 8'h48) & ~TransmitFIFOWriteFull & TransmitInactive);
else TransmitFIFOWriteIncrement <= (Memwrite & (Entry == SPI_TXDATA) & ~TransmitFIFOWriteFull);
always_ff @(posedge PCLK)
if (~PRESETn) ReceiveFIFOReadIncrement <= 1'b0;
else ReceiveFIFOReadIncrement <= ((Entry == 8'h4C) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
else ReceiveFIFOReadIncrement <= ((Entry == SPI_RXDATA) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
// Tx/Rx FIFOs
spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitShiftEmpty, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
@ -300,7 +303,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
always_ff @(posedge PCLK)
if (~PRESETn) begin
state <= CS_INACTIVE;
FrameCount <= 4'b0;
FrameCount <= 4'b0;
SPICLK <= SckMode[1];
end else if (SCLKenable) begin
/* verilator lint_off CASEINCOMPLETE */
case (state)
@ -311,21 +315,32 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
InterCSCount <= 9'b10;
InterXFRCount <= 9'b1;
if ((~TransmitFIFOReadEmpty | ~TransmitShiftEmpty) & ((|(Delay0[7:0])) | ~SckMode[0])) state <= DELAY_0;
else if ((~TransmitFIFOReadEmpty | ~TransmitShiftEmpty)) state <= ACTIVE_0;
else if ((~TransmitFIFOReadEmpty | ~TransmitShiftEmpty)) begin
state <= ACTIVE_0;
SPICLK <= ~SckMode[1];
end else SPICLK <= SckMode[1];
end
DELAY_0: begin
CS_SCKCount <= CS_SCKCount + 9'b1;
if (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1)) state <= ACTIVE_0;
if (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1)) begin
state <= ACTIVE_0;
SPICLK <= ~SckMode[1];
end
end
ACTIVE_0: begin
FrameCount <= FrameCount + 4'b1;
SPICLK <= SckMode[1];
state <= ACTIVE_1;
end
ACTIVE_1: begin
InterXFRCount <= 9'b1;
if (FrameCount < Format[4:1]) state <= ACTIVE_0;
if (FrameCount < Format[4:1]) begin
state <= ACTIVE_0;
SPICLK <= ~SckMode[1];
end
else if ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty)) begin
state <= ACTIVE_0;
SPICLK <= ~SckMode[1];
CS_SCKCount <= 9'b1;
SCK_CSCount <= 9'b10;
FrameCount <= 4'b0;
@ -341,6 +356,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
end
INTER_CS: begin
InterCSCount <= InterCSCount + 9'b1;
SPICLK <= SckMode[1];
if (InterCSCount >= ({Delay1[7:0],1'b0})) state <= CS_INACTIVE;
end
INTER_XFR: begin
@ -349,8 +365,11 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
FrameCount <= 4'b0;
InterCSCount <= 9'b10;
InterXFRCount <= InterXFRCount + 9'b1;
if ((InterXFRCount >= ({Delay1[15:8], 1'b0})) & ~TransmitFIFOReadEmptyDelay) state <= ACTIVE_0;
else if (~|ChipSelectMode[1:0]) state <= CS_INACTIVE;
if ((InterXFRCount >= ({Delay1[15:8], 1'b0})) & ~TransmitFIFOReadEmptyDelay) begin
state <= ACTIVE_0;
SPICLK <= ~SckMode[1];
end else if (~|ChipSelectMode[1:0]) state <= CS_INACTIVE;
else SPICLK <= SckMode[1];
end
endcase
/* verilator lint_off CASEINCOMPLETE */
@ -360,32 +379,28 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
assign DelayMode = SckMode[0] ? (state == DELAY_1) : (state == ACTIVE_1 & ReceiveShiftFull);
assign ChipSelectInternal = (state == CS_INACTIVE | state == INTER_CS | DelayMode & ~|(Delay0[15:8])) ? ChipSelectDef : ~ChipSelectDef;
assign SPICLK = (state == ACTIVE_0) ? ~SckMode[1] : SckMode[1];
assign Active = (state == ACTIVE_0 | state == ACTIVE_1);
assign SampleEdge = SckMode[0] ? (state == ACTIVE_1) : (state == ACTIVE_0);
assign ZeroDelayHoldMode = ((ChipSelectMode == 2'b10) & (~|(Delay1[7:4])));
assign TransmitInactive = ((state == INTER_CS) | (state == CS_INACTIVE) | (state == INTER_XFR) | (ReceiveShiftFullDelayPCLK & ZeroDelayHoldMode));
assign TransmitInactive = ((state == INTER_CS) | (state == CS_INACTIVE) | (state == INTER_XFR) | (ReceiveShiftFullDelayPCLK & ZeroDelayHoldMode) | ((state == ACTIVE_1) & ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty) & (FrameCount == Format[4:1]))));
assign Active0 = (state == ACTIVE_0);
// Signal tracks which edge of sck to shift data
// Jacob: We need to confirm that this represents the actual polarity and phase options for sampling.
// The first option now samples on the leading edge and shifts on the falling edge like it's supposed to.
// We need to confirm the validity of the other options.
always_comb
case(SckMode[1:0])
2'b00: ShiftEdge = SPICLK & SCLKenable;
2'b01: ShiftEdge = (SPICLK & |(FrameCount) & SCLKenable); // Probably wrong
2'b10: ShiftEdge = ~SPICLK & SCLKenable; // Probably wrong
2'b11: ShiftEdge = (~SPICLK & |(FrameCount) & SCLKenable); // Probably wrong
2'b01: ShiftEdge = (~SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
2'b10: ShiftEdge = ~SPICLK & SCLKenable;
2'b11: ShiftEdge = (SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
default: ShiftEdge = SPICLK & SCLKenable;
endcase
// Transmit shift register
assign TransmitDataEndian = Format[0] ? {TransmitFIFOReadData[0], TransmitFIFOReadData[1], TransmitFIFOReadData[2], TransmitFIFOReadData[3], TransmitFIFOReadData[4], TransmitFIFOReadData[5], TransmitFIFOReadData[6], TransmitFIFOReadData[7]} : TransmitFIFOReadData[7:0];
always_ff @(posedge PCLK)
if(~PRESETn) TransmitShiftReg <= 8'b0; // Temporarily changing to 1s
if(~PRESETn) TransmitShiftReg <= 8'b0;
else if (TransmitShiftRegLoad) TransmitShiftReg <= TransmitDataEndian;
else if (ShiftEdge & Active) TransmitShiftReg <= {TransmitShiftReg[6:0], TransmitShiftReg[0]}; // Temporarily changing to 1s
else if (ShiftEdge & Active) TransmitShiftReg <= {TransmitShiftReg[6:0], TransmitShiftReg[0]};
assign SPIOut = TransmitShiftReg[7];

2
testbench/common/DCacheFlushFSM.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// DCacheFlushFSM.sv
//
// Written: David Harris David_Harris@hmc.edu and Ross Thompson ross1728@gmail.com
// Written: David Harris David_Harris@hmc.edu and Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023
//
// Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty

2
testbench/common/functionName.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// functionName.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
//
// Purpose: decode name of function
//

6
testbench/common/loggers.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// loggers.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023
//
// Purpose: Log branch instructions, log instruction fetches,
@ -246,8 +246,8 @@ module loggers import cvw::*; #(parameter cvw_t P,
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
initial begin
LogFile = "branch.log"; // will break some of Ross's research analysis scripts
CFILogFile = "cfi.log"; // will break some of Ross's research analysis scripts
LogFile = "branch.log"; // will break some of Rose's research analysis scripts
CFILogFile = "cfi.log"; // will break some of Rose's research analysis scripts
//LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
file = $fopen(LogFile, "w");
CFIfile = $fopen(CFILogFile, "w");

2
testbench/common/watchdog.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// watchdog.sv
//
// Written: Ross Thompson ross1728@gmail.com
// Written: Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023
//
// Purpose: Detects if the processor is stuck and halts the simulation

2
testbench/sdc/sdModel.sv
View File

@ -917,7 +917,7 @@ module sdModel
WRITE_DATA: begin
oeDat<=1;
outdly_cnt<=outdly_cnt+1;
datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Ross)
datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Rose)
if ( outdly_cnt > `DLY_TO_OUTP) begin // if (outdly_cnt > 47) NAC cycles elapsed

2
tests/custom/fpga-test-sdc/copyFlash.c
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// copyFlash.sv
//
// Written: Ross Thompson September 25, 2021
// Written: Rose Thompson September 25, 2021
// Modified:
//
// Purpose: copies flash card into memory

2
tests/custom/fpga-test-sdc/sdcDriver.c
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// SDC.sv
//
// Written: Ross Thompson September 25, 2021
// Written: Rose Thompson September 25, 2021
// Modified:
//
// Purpose: driver for sdc reader.

2
tests/custom/simple/fail.s
View File

@ -1,4 +1,4 @@
# Ross Thompson
# Rose Thompson
# March 17, 2021
# Oklahoma State University

34
tests/fp/Makefile Executable file
View File

@ -0,0 +1,34 @@
# Jordan Carlin, jcarlin@hmc.edu, August 2024
# Testfloat vector Makefile for CORE-V-Wally
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
SOFTFLOAT_DIR := ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC
TESTFLOAT_DIR := ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC
.PHONY: all softfloat testfloat vectors combined_IF_vectors clean
all: vectors combined_IF_vectors
softfloat: ${SOFTFLOAT_DIR}/softfloat.a
testfloat: ${TESTFLOAT_DIR}/testfloat
vectors: testfloat
$(MAKE) -C ${WALLY}/tests/fp/vectors
combined_IF_vectors: ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src vectors
cd ${WALLY}/tests/fp/combined_IF_vectors \
&& ./create_IF_vectors.sh
clean:
$(MAKE) -C ${WALLY}/tests/fp/vectors clean
rm -f ${WALLY}/tests/fp/combined_IF_vectors/IF_vectors/*.tv
${SOFTFLOAT_DIR}/softfloat.a:
$(MAKE) -C ${SOFTFLOAT_DIR}
${TESTFLOAT_DIR}/testfloat: ${SOFTFLOAT_DIR}/softfloat.a
$(MAKE) -C ${TESTFLOAT_DIR}
${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src:
@$(error "riscv-arch-tests must be generated first. Run make from $$WALLY")

328
tests/fp/README.md
View File

@ -1,187 +1,171 @@
james.stine@okstate.edu 14 Jan 2022
These are the testvectors (TV) to test the floating-point units using
These are the testvectors (TV) to test the floating-point unit using
Berkeley TestFloat written originally by John Hauser. TestFloat
requires both TestFloat and SoftFloat.
The locations at time of this README is found here:
The locations of these tools at time of this README is found here:
TestFloat-3e: http://www.jhauser.us/arithmetic/TestFloat.html
SoftFloat-3e: http://www.jhauser.us/arithmetic/SoftFloat.html
These files have been compiled on a x86_64 environment by going into
the build/Linux-x86_64-GCC directory and typing make. A script
createX.sh (e.g., create_vectors32.sh) has been included that create
the TV for each rounding mode and operation. These scripts must be
run in the build directory of TestFloat.
These tools have been compiled on a x86_64 environment by going into
their respective build/Linux-x86_64-GCC directories and running make.
A set of scripts is also include that runs everything from the
baseline directory. Please change the BUILD and OUTPUT variable to
change your baseline program where its compiled and where you want to
output the vectors. By default, the vectors are output into the
vectors subdirectory.
The makefile in the vectors subdirectory of this directory will generate TV
for each rounding mode and operation. It also puts an underscore between each
vector instead of a space to allow SystemVerilog readmemh to read correctly.
After each TV has been created a script (included) is run called
undy.sh that puts an underscore between vector to allow SystemVerilog
readmemh to read correctly.
./undy.sh file.tv
To remove all the underscores from all the TV files, one can run the
command that will add underscores appropriately to all the files.
cd vectors
../undy.sh \*
Note: due to size, the fxx_fma_xx.tv vectors are not included.
However, they can easily be created with the create scripts.
The makefile at the top level of this directory will compile SoftFloat and
TestFloat and then generate all of the TVs. It also generates TVs for the
combined integer floating-point divider.
Although not needed, a case.sh script is included to change the case
of the hex output. This is for those that do not like to see
hexadecimal capitalized :P.
hexadecimal capitalized :P.
46464 185856 836352 f16_add_rd.tv
46464 185856 836352 f16_add_rne.tv
46464 185856 836352 f16_add_ru.tv
46464 185856 836352 f16_add_rz.tv
46464 185856 836352 f16_div_rd.tv
46464 185856 836352 f16_div_rne.tv
46464 185856 836352 f16_div_ru.tv
46464 185856 836352 f16_div_rz.tv
46464 185856 836352 f16_mul_rd.tv
46464 185856 836352 f16_mul_rne.tv
46464 185856 836352 f16_mul_ru.tv
46464 185856 836352 f16_mul_rz.tv
408 1224 5304 f16_sqrt_rd.tv
408 1224 5304 f16_sqrt_rne.tv
408 1224 5304 f16_sqrt_ru.tv
408 1224 5304 f16_sqrt_rz.tv
46464 185856 836352 f16_sub_rd.tv
46464 185856 836352 f16_sub_rne.tv
46464 185856 836352 f16_sub_ru.tv
46464 185856 836352 f16_sub_rz.tv
46464 185856 1393920 f32_add_rd.tv
46464 185856 1393920 f32_add_rne.tv
46464 185856 1393920 f32_add_ru.tv
46464 185856 1393920 f32_add_rz.tv
46464 185856 1068672 f32_cmp_eq_signaling.tv
46464 185856 1068672 f32_cmp_eq.tv
46464 185856 1068672 f32_cmp_le_quiet.tv
46464 185856 1068672 f32_cmp_le.tv
46464 185856 1068672 f32_cmp_lt_quiet.tv
46464 185856 1068672 f32_cmp_lt.tv
46464 185856 1393920 f32_div_rd.tv
46464 185856 1393920 f32_div_rne.tv
46464 185856 1393920 f32_div_ru.tv
46464 185856 1393920 f32_div_rz.tv
600 1800 17400 f32_f64_rd.tv
600 1800 17400 f32_f64_rne.tv
600 1800 17400 f32_f64_ru.tv
600 1800 17400 f32_f64_rz.tv
600 1800 12600 f32_i32_rd.tv
600 1800 12600 f32_i32_rne.tv
600 1800 12600 f32_i32_ru.tv
600 1800 12600 f32_i32_rz.tv
600 1800 17400 f32_i64_rd.tv
600 1800 17400 f32_i64_rne.tv
600 1800 17400 f32_i64_ru.tv
600 1800 17400 f32_i64_rz.tv
46464 185856 1393920 f32_mul_rd.tv
46464 185856 1393920 f32_mul_rne.tv
46464 185856 1393920 f32_mul_ru.tv
46464 185856 1393920 f32_mul_rz.tv
600 1800 12600 f32_sqrt_rd.tv
600 1800 12600 f32_sqrt_rne.tv
600 1800 12600 f32_sqrt_ru.tv
600 1800 12600 f32_sqrt_rz.tv
46464 185856 1393920 f32_sub_rd.tv
46464 185856 1393920 f32_sub_rne.tv
46464 185856 1393920 f32_sub_ru.tv
46464 185856 1393920 f32_sub_rz.tv
600 1800 12600 f32_ui32_rd.tv
600 1800 12600 f32_ui32_rne.tv
600 1800 12600 f32_ui32_ru.tv
600 1800 12600 f32_ui32_rz.tv
600 1800 17400 f32_ui64_rd.tv
600 1800 17400 f32_ui64_rne.tv
600 1800 17400 f32_ui64_ru.tv
600 1800 17400 f32_ui64_rz.tv
46464 185856 2509056 f64_add_rd.tv
46464 185856 2509056 f64_add_rne.tv
46464 185856 2509056 f64_add_ru.tv
46464 185856 2509056 f64_add_rz.tv
46464 185856 1812096 f64_cmp_eq_signaling.tv
46464 185856 1812096 f64_cmp_eq.tv
46464 185856 1812096 f64_cmp_le_quiet.tv
46464 185856 1812096 f64_cmp_le.tv
46464 185856 1812096 f64_cmp_lt_quiet.tv
46464 185856 1812096 f64_cmp_lt.tv
46464 185856 2509056 f64_div_rd.tv
46464 185856 2509056 f64_div_rne.tv
46464 185856 2509056 f64_div_ru.tv
46464 185856 2509056 f64_div_rz.tv
768 2304 22272 f64_f32_rd.tv
768 2304 22272 f64_f32_rne.tv
768 2304 22272 f64_f32_ru.tv
768 2304 22272 f64_f32_rz.tv
768 2304 22272 f64_i32_rd.tv
768 2304 22272 f64_i32_rne.tv
768 2304 22272 f64_i32_ru.tv
768 2304 22272 f64_i32_rz.tv
768 2304 28416 f64_i64_rd.tv
768 2304 28416 f64_i64_rne.tv
768 2304 28416 f64_i64_ru.tv
768 2304 28416 f64_i64_rz.tv
46464 185856 2509056 f64_mul_rd.tv
46464 185856 2509056 f64_mul_rne.tv
46464 185856 2509056 f64_mul_ru.tv
46464 185856 2509056 f64_mul_rz.tv
768 2304 28416 f64_sqrt_rd.tv
768 2304 28416 f64_sqrt_rne.tv
768 2304 28416 f64_sqrt_ru.tv
768 2304 28416 f64_sqrt_rz.tv
46464 185856 2509056 f64_sub_rd.tv
46464 185856 2509056 f64_sub_rne.tv
46464 185856 2509056 f64_sub_ru.tv
46464 185856 2509056 f64_sub_rz.tv
768 2304 22272 f64_ui32_rd.tv
768 2304 22272 f64_ui32_rne.tv
768 2304 22272 f64_ui32_ru.tv
768 2304 22272 f64_ui32_rz.tv
768 2304 28416 f64_ui64_rd.tv
768 2304 28416 f64_ui64_rne.tv
768 2304 28416 f64_ui64_ru.tv
768 2304 28416 f64_ui64_rz.tv
372 1116 7812 i32_f32_rd.tv
372 1116 7812 i32_f32_rne.tv
372 1116 7812 i32_f32_ru.tv
372 1116 7812 i32_f32_rz.tv
372 1116 10788 i32_f64_rd.tv
372 1116 10788 i32_f64_rne.tv
372 1116 10788 i32_f64_ru.tv
372 1116 10788 i32_f64_rz.tv
756 2268 21924 i64_f32_rd.tv
756 2268 21924 i64_f32_rne.tv
756 2268 21924 i64_f32_ru.tv
756 2268 21924 i64_f32_rz.tv
756 2268 27972 i64_f64_rd.tv
756 2268 27972 i64_f64_rne.tv
756 2268 27972 i64_f64_ru.tv
756 2268 27972 i64_f64_rz.tv
372 1116 7812 ui32_f32_rd.tv
372 1116 7812 ui32_f32_rne.tv
372 1116 7812 ui32_f32_ru.tv
372 1116 7812 ui32_f32_rz.tv
372 1116 10788 ui32_f64_rd.tv
372 1116 10788 ui32_f64_rne.tv
372 1116 10788 ui32_f64_ru.tv
372 1116 10788 ui32_f64_rz.tv
756 2268 21924 ui64_f32_rd.tv
756 2268 21924 ui64_f32_rne.tv
756 2268 21924 ui64_f32_ru.tv
756 2268 21924 ui64_f32_rz.tv
756 2268 27972 ui64_f64_rd.tv
756 2268 27972 ui64_f64_rne.tv
756 2268 27972 ui64_f64_ru.tv
756 2268 27972 ui64_f64_rz.tv
2840352 11308896 94651296 total
46464 185856 836352 f16_add_rd.tv
46464 185856 836352 f16_add_rne.tv
46464 185856 836352 f16_add_ru.tv
46464 185856 836352 f16_add_rz.tv
46464 185856 836352 f16_div_rd.tv
46464 185856 836352 f16_div_rne.tv
46464 185856 836352 f16_div_ru.tv
46464 185856 836352 f16_div_rz.tv
46464 185856 836352 f16_mul_rd.tv
46464 185856 836352 f16_mul_rne.tv
46464 185856 836352 f16_mul_ru.tv
46464 185856 836352 f16_mul_rz.tv
408 1224 5304 f16_sqrt_rd.tv
408 1224 5304 f16_sqrt_rne.tv
408 1224 5304 f16_sqrt_ru.tv
408 1224 5304 f16_sqrt_rz.tv
46464 185856 836352 f16_sub_rd.tv
46464 185856 836352 f16_sub_rne.tv
46464 185856 836352 f16_sub_ru.tv
46464 185856 836352 f16_sub_rz.tv
46464 185856 1393920 f32_add_rd.tv
46464 185856 1393920 f32_add_rne.tv
46464 185856 1393920 f32_add_ru.tv
46464 185856 1393920 f32_add_rz.tv
46464 185856 1068672 f32_cmp_eq_signaling.tv
46464 185856 1068672 f32_cmp_eq.tv
46464 185856 1068672 f32_cmp_le_quiet.tv
46464 185856 1068672 f32_cmp_le.tv
46464 185856 1068672 f32_cmp_lt_quiet.tv
46464 185856 1068672 f32_cmp_lt.tv
46464 185856 1393920 f32_div_rd.tv
46464 185856 1393920 f32_div_rne.tv
46464 185856 1393920 f32_div_ru.tv
46464 185856 1393920 f32_div_rz.tv
600 1800 17400 f32_f64_rd.tv
600 1800 17400 f32_f64_rne.tv
600 1800 17400 f32_f64_ru.tv
600 1800 17400 f32_f64_rz.tv
600 1800 12600 f32_i32_rd.tv
600 1800 12600 f32_i32_rne.tv
600 1800 12600 f32_i32_ru.tv
600 1800 12600 f32_i32_rz.tv
600 1800 17400 f32_i64_rd.tv
600 1800 17400 f32_i64_rne.tv
600 1800 17400 f32_i64_ru.tv
600 1800 17400 f32_i64_rz.tv
46464 185856 1393920 f32_mul_rd.tv
46464 185856 1393920 f32_mul_rne.tv
46464 185856 1393920 f32_mul_ru.tv
46464 185856 1393920 f32_mul_rz.tv
600 1800 12600 f32_sqrt_rd.tv
600 1800 12600 f32_sqrt_rne.tv
600 1800 12600 f32_sqrt_ru.tv
600 1800 12600 f32_sqrt_rz.tv
46464 185856 1393920 f32_sub_rd.tv
46464 185856 1393920 f32_sub_rne.tv
46464 185856 1393920 f32_sub_ru.tv
46464 185856 1393920 f32_sub_rz.tv
600 1800 12600 f32_ui32_rd.tv
600 1800 12600 f32_ui32_rne.tv
600 1800 12600 f32_ui32_ru.tv
600 1800 12600 f32_ui32_rz.tv
600 1800 17400 f32_ui64_rd.tv
600 1800 17400 f32_ui64_rne.tv
600 1800 17400 f32_ui64_ru.tv
600 1800 17400 f32_ui64_rz.tv
46464 185856 2509056 f64_add_rd.tv
46464 185856 2509056 f64_add_rne.tv
46464 185856 2509056 f64_add_ru.tv
46464 185856 2509056 f64_add_rz.tv
46464 185856 1812096 f64_cmp_eq_signaling.tv
46464 185856 1812096 f64_cmp_eq.tv
46464 185856 1812096 f64_cmp_le_quiet.tv
46464 185856 1812096 f64_cmp_le.tv
46464 185856 1812096 f64_cmp_lt_quiet.tv
46464 185856 1812096 f64_cmp_lt.tv
46464 185856 2509056 f64_div_rd.tv
46464 185856 2509056 f64_div_rne.tv
46464 185856 2509056 f64_div_ru.tv
46464 185856 2509056 f64_div_rz.tv
768 2304 22272 f64_f32_rd.tv
768 2304 22272 f64_f32_rne.tv
768 2304 22272 f64_f32_ru.tv
768 2304 22272 f64_f32_rz.tv
768 2304 22272 f64_i32_rd.tv
768 2304 22272 f64_i32_rne.tv
768 2304 22272 f64_i32_ru.tv
768 2304 22272 f64_i32_rz.tv
768 2304 28416 f64_i64_rd.tv
768 2304 28416 f64_i64_rne.tv
768 2304 28416 f64_i64_ru.tv
768 2304 28416 f64_i64_rz.tv
46464 185856 2509056 f64_mul_rd.tv
46464 185856 2509056 f64_mul_rne.tv
46464 185856 2509056 f64_mul_ru.tv
46464 185856 2509056 f64_mul_rz.tv
768 2304 28416 f64_sqrt_rd.tv
768 2304 28416 f64_sqrt_rne.tv
768 2304 28416 f64_sqrt_ru.tv
768 2304 28416 f64_sqrt_rz.tv
46464 185856 2509056 f64_sub_rd.tv
46464 185856 2509056 f64_sub_rne.tv
46464 185856 2509056 f64_sub_ru.tv
46464 185856 2509056 f64_sub_rz.tv
768 2304 22272 f64_ui32_rd.tv
768 2304 22272 f64_ui32_rne.tv
768 2304 22272 f64_ui32_ru.tv
768 2304 22272 f64_ui32_rz.tv
768 2304 28416 f64_ui64_rd.tv
768 2304 28416 f64_ui64_rne.tv
768 2304 28416 f64_ui64_ru.tv
768 2304 28416 f64_ui64_rz.tv
372 1116 7812 i32_f32_rd.tv
372 1116 7812 i32_f32_rne.tv
372 1116 7812 i32_f32_ru.tv
372 1116 7812 i32_f32_rz.tv
372 1116 10788 i32_f64_rd.tv
372 1116 10788 i32_f64_rne.tv
372 1116 10788 i32_f64_ru.tv
372 1116 10788 i32_f64_rz.tv
756 2268 21924 i64_f32_rd.tv
756 2268 21924 i64_f32_rne.tv
756 2268 21924 i64_f32_ru.tv
756 2268 21924 i64_f32_rz.tv
756 2268 27972 i64_f64_rd.tv
756 2268 27972 i64_f64_rne.tv
756 2268 27972 i64_f64_ru.tv
756 2268 27972 i64_f64_rz.tv
372 1116 7812 ui32_f32_rd.tv
372 1116 7812 ui32_f32_rne.tv
372 1116 7812 ui32_f32_ru.tv
372 1116 7812 ui32_f32_rz.tv
372 1116 10788 ui32_f64_rd.tv
372 1116 10788 ui32_f64_rne.tv
372 1116 10788 ui32_f64_ru.tv
372 1116 10788 ui32_f64_rz.tv
756 2268 21924 ui64_f32_rd.tv
756 2268 21924 ui64_f32_rne.tv
756 2268 21924 ui64_f32_ru.tv
756 2268 21924 ui64_f32_rz.tv
756 2268 27972 ui64_f64_rd.tv
756 2268 27972 ui64_f64_rne.tv
756 2268 27972 ui64_f64_ru.tv
756 2268 27972 ui64_f64_rz.tv
2840352 11308896 94651296 total

8
tests/fp/create_all_vectors.sh
View File

@ -1,8 +0,0 @@
#!/bin/sh
mkdir -p vectors
./create_vectors.sh
./remove_spaces.sh
# to create tvs for evaluation of combined IFdivsqrt
cd combined_IF_vectors; ./create_IF_vectors.sh

483
tests/fp/create_vectors.sh
View File

@ -1,483 +0,0 @@
#!/bin/sh
BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
OUTPUT="./vectors"
echo "Creating ui32_to_f16 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f16 > $OUTPUT/ui32_to_f16_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f16 > $OUTPUT/ui32_to_f16_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f16 > $OUTPUT/ui32_to_f16_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rnm.tv
echo "Creating ui32_to_f32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f32 > $OUTPUT/ui32_to_f32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f32 > $OUTPUT/ui32_to_f32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f32 > $OUTPUT/ui32_to_f32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rnm.tv
echo "Creating ui32_to_f64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f64 > $OUTPUT/ui32_to_f64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f64 > $OUTPUT/ui32_to_f64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f64 > $OUTPUT/ui32_to_f64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rnm.tv
echo "Creating ui32_to_f128 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f128 > $OUTPUT/ui32_to_f128_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f128 > $OUTPUT/ui32_to_f128_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f128 > $OUTPUT/ui32_to_f128_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rnm.tv
echo "Creating ui64_to_f16 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f16 > $OUTPUT/ui64_to_f16_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f16 > $OUTPUT/ui64_to_f16_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f16 > $OUTPUT/ui64_to_f16_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rnm.tv
echo "Creating ui64_to_f32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f32 > $OUTPUT/ui64_to_f32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f32 > $OUTPUT/ui64_to_f32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f32 > $OUTPUT/ui64_to_f32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rnm.tv
echo "Creating ui64_to_f64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f64 > $OUTPUT/ui64_to_f64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f64 > $OUTPUT/ui64_to_f64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f64 > $OUTPUT/ui64_to_f64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rnm.tv
echo "Creating ui64_to_f128 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f128 > $OUTPUT/ui64_to_f128_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f128 > $OUTPUT/ui64_to_f128_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f128 > $OUTPUT/ui64_to_f128_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rnm.tv
echo "Creating i32_to_f16 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f16 > $OUTPUT/i32_to_f16_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f16 > $OUTPUT/i32_to_f16_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f16 > $OUTPUT/i32_to_f16_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f16 > $OUTPUT/i32_to_f16_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f16 > $OUTPUT/i32_to_f16_rnm.tv
echo "Creating i32_to_f32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f32 > $OUTPUT/i32_to_f32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f32 > $OUTPUT/i32_to_f32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f32 > $OUTPUT/i32_to_f32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f32 > $OUTPUT/i32_to_f32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f32 > $OUTPUT/i32_to_f32_rnm.tv
echo "Creating i32_to_f64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f64 > $OUTPUT/i32_to_f64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f64 > $OUTPUT/i32_to_f64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f64 > $OUTPUT/i32_to_f64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f64 > $OUTPUT/i32_to_f64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f64 > $OUTPUT/i32_to_f64_rnm.tv
echo "Creating i32_to_f128 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f128 > $OUTPUT/i32_to_f128_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f128 > $OUTPUT/i32_to_f128_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f128 > $OUTPUT/i32_to_f128_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f128 > $OUTPUT/i32_to_f128_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f128 > $OUTPUT/i32_to_f128_rnm.tv
echo "Creating i64_to_f16 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f16 > $OUTPUT/i64_to_f16_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f16 > $OUTPUT/i64_to_f16_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f16 > $OUTPUT/i64_to_f16_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f16 > $OUTPUT/i64_to_f16_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f16 > $OUTPUT/i64_to_f16_rnm.tv
echo "Creating i64_to_f32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f32 > $OUTPUT/i64_to_f32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f32 > $OUTPUT/i64_to_f32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f32 > $OUTPUT/i64_to_f32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f32 > $OUTPUT/i64_to_f32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f32 > $OUTPUT/i64_to_f32_rnm.tv
echo "Creating i64_to_f64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f64 > $OUTPUT/i64_to_f64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f64 > $OUTPUT/i64_to_f64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f64 > $OUTPUT/i64_to_f64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f64 > $OUTPUT/i64_to_f64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f64 > $OUTPUT/i64_to_f64_rnm.tv
echo "Creating i64_to_f128 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f128 > $OUTPUT/i64_to_f128_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f128 > $OUTPUT/i64_to_f128_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f128 > $OUTPUT/i64_to_f128_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f128 > $OUTPUT/i64_to_f128_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f128 > $OUTPUT/i64_to_f128_rnm.tv
echo "Creating f16_to_ui32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui32 > $OUTPUT/f16_to_ui32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui32 > $OUTPUT/f16_to_ui32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui32 > $OUTPUT/f16_to_ui32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rnm.tv
echo "Creating f32_to_ui32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui32 > $OUTPUT/f32_to_ui32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui32 > $OUTPUT/f32_to_ui32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui32 > $OUTPUT/f32_to_ui32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rnm.tv
echo "Creating f64_to_ui32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui32 > $OUTPUT/f64_to_ui32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui32 > $OUTPUT/f64_to_ui32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui32 > $OUTPUT/f64_to_ui32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rnm.tv
echo "Creating f128_to_ui32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui32 > $OUTPUT/f128_to_ui32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui32 > $OUTPUT/f128_to_ui32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui32 > $OUTPUT/f128_to_ui32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rnm.tv
echo "Creating f16_to_ui64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui64 > $OUTPUT/f16_to_ui64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui64 > $OUTPUT/f16_to_ui64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui64 > $OUTPUT/f16_to_ui64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rnm.tv
echo "Creating f32_to_ui64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui64 > $OUTPUT/f32_to_ui64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui64 > $OUTPUT/f32_to_ui64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui64 > $OUTPUT/f32_to_ui64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rnm.tv
echo "Creating f64_to_ui64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui64 > $OUTPUT/f64_to_ui64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui64 > $OUTPUT/f64_to_ui64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui64 > $OUTPUT/f64_to_ui64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rnm.tv
echo "Creating f128_to_ui64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui64 > $OUTPUT/f128_to_ui64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui64 > $OUTPUT/f128_to_ui64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui64 > $OUTPUT/f128_to_ui64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rnm.tv
echo "Creating f16_to_i32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i32 > $OUTPUT/f16_to_i32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i32 > $OUTPUT/f16_to_i32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i32 > $OUTPUT/f16_to_i32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i32 > $OUTPUT/f16_to_i32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i32 > $OUTPUT/f16_to_i32_rnm.tv
echo "Creating f32_to_i32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i32 > $OUTPUT/f32_to_i32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i32 > $OUTPUT/f32_to_i32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i32 > $OUTPUT/f32_to_i32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i32 > $OUTPUT/f32_to_i32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i32 > $OUTPUT/f32_to_i32_rnm.tv
echo "Creating f64_to_i32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i32 > $OUTPUT/f64_to_i32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i32 > $OUTPUT/f64_to_i32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i32 > $OUTPUT/f64_to_i32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i32 > $OUTPUT/f64_to_i32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i32 > $OUTPUT/f64_to_i32_rnm.tv
echo "Creating f128_to_i32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i32 > $OUTPUT/f128_to_i32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i32 > $OUTPUT/f128_to_i32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i32 > $OUTPUT/f128_to_i32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i32 > $OUTPUT/f128_to_i32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i32 > $OUTPUT/f128_to_i32_rnm.tv
echo "Creating f16_to_i64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i64 > $OUTPUT/f16_to_i64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i64 > $OUTPUT/f16_to_i64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i64 > $OUTPUT/f16_to_i64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i64 > $OUTPUT/f16_to_i64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i64 > $OUTPUT/f16_to_i64_rnm.tv
echo "Creating f32_to_i64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i64 > $OUTPUT/f32_to_i64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i64 > $OUTPUT/f32_to_i64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i64 > $OUTPUT/f32_to_i64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i64 > $OUTPUT/f32_to_i64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i64 > $OUTPUT/f32_to_i64_rnm.tv
echo "Creating f64_to_i64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i64 > $OUTPUT/f64_to_i64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i64 > $OUTPUT/f64_to_i64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i64 > $OUTPUT/f64_to_i64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i64 > $OUTPUT/f64_to_i64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i64 > $OUTPUT/f64_to_i64_rnm.tv
echo "Creating f128_to_i64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i64 > $OUTPUT/f128_to_i64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i64 > $OUTPUT/f128_to_i64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i64 > $OUTPUT/f128_to_i64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i64 > $OUTPUT/f128_to_i64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i64 > $OUTPUT/f128_to_i64_rnm.tv
echo "Creating f16_to_f32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f32 > $OUTPUT/f16_to_f32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f32 > $OUTPUT/f16_to_f32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f32 > $OUTPUT/f16_to_f32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f32 > $OUTPUT/f16_to_f32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f32 > $OUTPUT/f16_to_f32_rnm.tv
echo "Creating f16_to_f64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f64 > $OUTPUT/f16_to_f64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f64 > $OUTPUT/f16_to_f64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f64 > $OUTPUT/f16_to_f64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f64 > $OUTPUT/f16_to_f64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f64 > $OUTPUT/f16_to_f64_rnm.tv
echo "Creating f16_to_f128 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f128 > $OUTPUT/f16_to_f128_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f128 > $OUTPUT/f16_to_f128_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f128 > $OUTPUT/f16_to_f128_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f128 > $OUTPUT/f16_to_f128_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f128 > $OUTPUT/f16_to_f128_rnm.tv
echo "Creating f32_to_f16 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f16 > $OUTPUT/f32_to_f16_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f16 > $OUTPUT/f32_to_f16_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f16 > $OUTPUT/f32_to_f16_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f16 > $OUTPUT/f32_to_f16_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f16 > $OUTPUT/f32_to_f16_rnm.tv
echo "Creating f32_to_f64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f64 > $OUTPUT/f32_to_f64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f64 > $OUTPUT/f32_to_f64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f64 > $OUTPUT/f32_to_f64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f64 > $OUTPUT/f32_to_f64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f64 > $OUTPUT/f32_to_f64_rnm.tv
echo "Creating f32_to_f128 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f128 > $OUTPUT/f32_to_f128_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f128 > $OUTPUT/f32_to_f128_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f128 > $OUTPUT/f32_to_f128_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f128 > $OUTPUT/f32_to_f128_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f128 > $OUTPUT/f32_to_f128_rnm.tv
echo "Creating f64_to_f16 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f16 > $OUTPUT/f64_to_f16_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f16 > $OUTPUT/f64_to_f16_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f16 > $OUTPUT/f64_to_f16_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f16 > $OUTPUT/f64_to_f16_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f16 > $OUTPUT/f64_to_f16_rnm.tv
echo "Creating f64_to_f32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f32 > $OUTPUT/f64_to_f32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f32 > $OUTPUT/f64_to_f32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f32 > $OUTPUT/f64_to_f32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f32 > $OUTPUT/f64_to_f32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f32 > $OUTPUT/f64_to_f32_rnm.tv
echo "Creating f64_to_f128 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f128 > $OUTPUT/f64_to_f128_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f128 > $OUTPUT/f64_to_f128_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f128 > $OUTPUT/f64_to_f128_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f128 > $OUTPUT/f64_to_f128_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f128 > $OUTPUT/f64_to_f128_rnm.tv
echo "Creating f128_to_f16 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f16 > $OUTPUT/f128_to_f16_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f16 > $OUTPUT/f128_to_f16_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f16 > $OUTPUT/f128_to_f16_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f16 > $OUTPUT/f128_to_f16_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f16 > $OUTPUT/f128_to_f16_rnm.tv
echo "Creating f128_to_f32 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f32 > $OUTPUT/f128_to_f32_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f32 > $OUTPUT/f128_to_f32_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f32 > $OUTPUT/f128_to_f32_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f32 > $OUTPUT/f128_to_f32_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f32 > $OUTPUT/f128_to_f32_rnm.tv
echo "Creating f128_to_f64 convert vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f64 > $OUTPUT/f128_to_f64_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f64 > $OUTPUT/f128_to_f64_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f64 > $OUTPUT/f128_to_f64_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f64 > $OUTPUT/f128_to_f64_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f64 > $OUTPUT/f128_to_f64_rnm.tv
echo "Creating f16_add vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_add > $OUTPUT/f16_add_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_add > $OUTPUT/f16_add_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_add > $OUTPUT/f16_add_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_add > $OUTPUT/f16_add_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_add > $OUTPUT/f16_add_rnm.tv
echo "Creating f32_add vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_add > $OUTPUT/f32_add_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_add > $OUTPUT/f32_add_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_add > $OUTPUT/f32_add_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_add > $OUTPUT/f32_add_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_add > $OUTPUT/f32_add_rnm.tv
echo "Creating f64_add vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_add > $OUTPUT/f64_add_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_add > $OUTPUT/f64_add_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_add > $OUTPUT/f64_add_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_add > $OUTPUT/f64_add_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_add > $OUTPUT/f64_add_rnm.tv
echo "Creating f128_add vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_add > $OUTPUT/f128_add_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_add > $OUTPUT/f128_add_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_add > $OUTPUT/f128_add_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_add > $OUTPUT/f128_add_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_add > $OUTPUT/f128_add_rnm.tv
echo "Creating f16_sub vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_sub > $OUTPUT/f16_sub_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_sub > $OUTPUT/f16_sub_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_sub > $OUTPUT/f16_sub_rnm.tv
echo "Creating f32_sub vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_sub > $OUTPUT/f32_sub_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_sub > $OUTPUT/f32_sub_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_sub > $OUTPUT/f32_sub_rnm.tv
echo "Creating f64_sub vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_sub > $OUTPUT/f64_sub_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_sub > $OUTPUT/f64_sub_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_sub > $OUTPUT/f64_sub_rnm.tv
echo "Creating f128_sub vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_sub > $OUTPUT/f128_sub_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_sub > $OUTPUT/f128_sub_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_sub > $OUTPUT/f128_sub_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_sub > $OUTPUT/f128_sub_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_sub > $OUTPUT/f128_sub_rnm.tv
echo "Creating f16_mul vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mul > $OUTPUT/f16_mul_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mul > $OUTPUT/f16_mul_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mul > $OUTPUT/f16_mul_rnm.tv
echo "Creating f32_mul vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mul > $OUTPUT/f32_mul_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mul > $OUTPUT/f32_mul_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mul > $OUTPUT/f32_mul_rnm.tv
echo "Creating f64_mul vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mul > $OUTPUT/f64_mul_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mul > $OUTPUT/f64_mul_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mul > $OUTPUT/f64_mul_rnm.tv
echo "Creating f128_mul vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mul > $OUTPUT/f128_mul_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mul > $OUTPUT/f128_mul_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mul > $OUTPUT/f128_mul_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mul > $OUTPUT/f128_mul_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mul > $OUTPUT/f128_mul_rnm.tv
echo "Creating f16_div vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_div > $OUTPUT/f16_div_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_div > $OUTPUT/f16_div_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_div > $OUTPUT/f16_div_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_div > $OUTPUT/f16_div_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_div > $OUTPUT/f16_div_rnm.tv
echo "Creating f32_div vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_div > $OUTPUT/f32_div_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_div > $OUTPUT/f32_div_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_div > $OUTPUT/f32_div_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_div > $OUTPUT/f32_div_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_div > $OUTPUT/f32_div_rnm.tv
echo "Creating f64_div vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_div > $OUTPUT/f64_div_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_div > $OUTPUT/f64_div_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_div > $OUTPUT/f64_div_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_div > $OUTPUT/f64_div_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_div > $OUTPUT/f64_div_rnm.tv
echo "Creating f128_div vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_div > $OUTPUT/f128_div_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_div > $OUTPUT/f128_div_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_div > $OUTPUT/f128_div_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_div > $OUTPUT/f128_div_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_div > $OUTPUT/f128_div_rnm.tv
echo "Creating f16_sqrt vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_sqrt > $OUTPUT/f16_sqrt_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_sqrt > $OUTPUT/f16_sqrt_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_sqrt > $OUTPUT/f16_sqrt_rnm.tv
echo "Creating f32_sqrt vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_sqrt > $OUTPUT/f32_sqrt_rnm.tv
echo "Creating f64_sqrt vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_sqrt > $OUTPUT/f64_sqrt_rnm.tv
echo "Creating f128_sqrt vectors"
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_sqrt > $OUTPUT/f128_sqrt_rne.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_sqrt > $OUTPUT/f128_sqrt_rz.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_sqrt > $OUTPUT/f128_sqrt_ru.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_sqrt > $OUTPUT/f128_sqrt_rd.tv
$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_sqrt > $OUTPUT/f128_sqrt_rnm.tv
echo "Creating f16_eq vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_eq > $OUTPUT/f16_eq_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_eq > $OUTPUT/f16_eq_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_eq > $OUTPUT/f16_eq_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_eq > $OUTPUT/f16_eq_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_eq > $OUTPUT/f16_eq_rnm.tv
echo "Creating f32_eq vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_eq > $OUTPUT/f32_eq_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_eq > $OUTPUT/f32_eq_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_eq > $OUTPUT/f32_eq_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_eq > $OUTPUT/f32_eq_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_eq > $OUTPUT/f32_eq_rnm.tv
echo "Creating f64_eq vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_eq > $OUTPUT/f64_eq_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_eq > $OUTPUT/f64_eq_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_eq > $OUTPUT/f64_eq_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_eq > $OUTPUT/f64_eq_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_eq > $OUTPUT/f64_eq_rnm.tv
echo "Creating f128_eq vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_eq > $OUTPUT/f128_eq_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_eq > $OUTPUT/f128_eq_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_eq > $OUTPUT/f128_eq_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_eq > $OUTPUT/f128_eq_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_eq > $OUTPUT/f128_eq_rnm.tv
echo "Creating f16_le vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_le > $OUTPUT/f16_le_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_le > $OUTPUT/f16_le_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_le > $OUTPUT/f16_le_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_le > $OUTPUT/f16_le_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_le > $OUTPUT/f16_le_rnm.tv
echo "Creating f32_le vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_le > $OUTPUT/f32_le_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_le > $OUTPUT/f32_le_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_le > $OUTPUT/f32_le_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_le > $OUTPUT/f32_le_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_le > $OUTPUT/f32_le_rnm.tv
echo "Creating f64_le vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_le > $OUTPUT/f64_le_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_le > $OUTPUT/f64_le_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_le > $OUTPUT/f64_le_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_le > $OUTPUT/f64_le_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_le > $OUTPUT/f64_le_rnm.tv
echo "Creating f128_le vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_le > $OUTPUT/f128_le_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_le > $OUTPUT/f128_le_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_le > $OUTPUT/f128_le_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_le > $OUTPUT/f128_le_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_le > $OUTPUT/f128_le_rnm.tv
echo "Creating f16_lt vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_lt > $OUTPUT/f16_lt_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_lt > $OUTPUT/f16_lt_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_lt > $OUTPUT/f16_lt_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_lt > $OUTPUT/f16_lt_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_lt > $OUTPUT/f16_lt_rnm.tv
echo "Creating f32_lt vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_lt > $OUTPUT/f32_lt_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_lt > $OUTPUT/f32_lt_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_lt > $OUTPUT/f32_lt_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_lt > $OUTPUT/f32_lt_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_lt > $OUTPUT/f32_lt_rnm.tv
echo "Creating f64_lt vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_lt > $OUTPUT/f64_lt_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_lt > $OUTPUT/f64_lt_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_lt > $OUTPUT/f64_lt_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_lt > $OUTPUT/f64_lt_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_lt > $OUTPUT/f64_lt_rnm.tv
echo "Creating f128_lt vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_lt > $OUTPUT/f128_lt_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_lt > $OUTPUT/f128_lt_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_lt > $OUTPUT/f128_lt_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_lt > $OUTPUT/f128_lt_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_lt > $OUTPUT/f128_lt_rnm.tv
echo "Creating f16_mulAdd vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv
echo "Creating f32_mulAdd vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv
echo "Creating f64_mulAdd vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv
echo "Creating f128_mulAdd vectors"
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv
$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv

483
tests/fp/remove_spaces.sh
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@ -1,483 +0,0 @@
#!/bin/sh
BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
OUTPUT="./vectors"
echo "Editing ui32_to_f16 test vectors"
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rne.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rz.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_ru.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rd.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rnm.tv
echo "Editing ui32_to_f32 test vectors"
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rne.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rz.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_ru.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rd.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rnm.tv
echo "Editing ui32_to_f64 test vectors"
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rne.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rz.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_ru.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rd.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rnm.tv
echo "Editing ui32_to_f128 test vectors"
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rne.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rz.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_ru.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rd.tv
sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rnm.tv
echo "Editing ui64_to_f16 test vectors"
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rne.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rz.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_ru.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rd.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rnm.tv
echo "Editing ui64_to_f32 test vectors"
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rne.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rz.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_ru.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rd.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rnm.tv
echo "Editing ui64_to_f64 test vectors"
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rne.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rz.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_ru.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rd.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rnm.tv
echo "Editing ui64_to_f128 test vectors"
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rne.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rz.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_ru.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rd.tv
sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rnm.tv
echo "Editing i32_to_f16 test vectors"
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rne.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rz.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_ru.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rd.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rnm.tv
echo "Editing i32_to_f32 test vectors"
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rne.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rz.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_ru.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rd.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rnm.tv
echo "Editing i32_to_f64 test vectors"
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rne.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rz.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_ru.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rd.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rnm.tv
echo "Editing i32_to_f128 test vectors"
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rne.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rz.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_ru.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rd.tv
sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rnm.tv
echo "Editing i64_to_f16 test vectors"
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rne.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rz.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_ru.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rd.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rnm.tv
echo "Editing i64_to_f32 test vectors"
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rne.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rz.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_ru.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rd.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rnm.tv
echo "Editing i64_to_f64 test vectors"
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rne.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rz.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_ru.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rd.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rnm.tv
echo "Editing i64_to_f128 test vectors"
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rne.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rz.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_ru.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rd.tv
sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rnm.tv
echo "Editing f16_to_ui32 test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rnm.tv
echo "Editing f32_to_ui32 test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rnm.tv
echo "Editing f64_to_ui32 test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rnm.tv
echo "Editing f128_to_ui32 test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rnm.tv
echo "Editing f16_to_ui64 test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rnm.tv
echo "Editing f32_to_ui64 test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rnm.tv
echo "Editing f64_to_ui64 test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rnm.tv
echo "Editing f128_to_ui64 test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rnm.tv
echo "Editing f16_to_i32 test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rnm.tv
echo "Editing f32_to_i32 test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rnm.tv
echo "Editing f64_to_i32 test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rnm.tv
echo "Editing f128_to_i32 test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rnm.tv
echo "Editing f16_to_i64 test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rnm.tv
echo "Editing f32_to_i64 test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rnm.tv
echo "Editing f64_to_i64 test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rnm.tv
echo "Editing f128_to_i64 test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rnm.tv
echo "Editing f16_to_f32 test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rnm.tv
echo "Editing f16_to_f64 test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rnm.tv
echo "Editing f16_to_f128 test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rnm.tv
echo "Editing f32_to_f16 test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rnm.tv
echo "Editing f32_to_f64 test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rnm.tv
echo "Editing f32_to_f128 test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rnm.tv
echo "Editing f64_to_f16 test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rnm.tv
echo "Editing f64_to_f32 test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rnm.tv
echo "Editing f64_to_f128 test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rnm.tv
echo "Editing f128_to_f16 test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rnm.tv
echo "Editing f128_to_f32 test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rnm.tv
echo "Editing f128_to_f64 test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rnm.tv
echo "Editing f16_add test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_add_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_add_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_add_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_add_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_add_rnm.tv
echo "Editing f32_add test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_add_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_add_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_add_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_add_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_add_rnm.tv
echo "Editing f64_add test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_add_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_add_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_add_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_add_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_add_rnm.tv
echo "Editing f128_add test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_add_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_add_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_add_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_add_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_add_rnm.tv
echo "Editing f16_sub test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_sub_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_sub_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_sub_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_sub_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_sub_rnm.tv
echo "Editing f32_sub test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_sub_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_sub_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_sub_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_sub_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_sub_rnm.tv
echo "Editing f64_sub test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_sub_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_sub_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_sub_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_sub_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_sub_rnm.tv
echo "Editing f128_sub test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_sub_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_sub_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_sub_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_sub_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_sub_rnm.tv
echo "Editing f16_mul test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_mul_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_mul_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_mul_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_mul_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_mul_rnm.tv
echo "Editing f32_mul test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_mul_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_mul_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_mul_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_mul_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_mul_rnm.tv
echo "Editing f64_mul test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_mul_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_mul_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_mul_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_mul_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_mul_rnm.tv
echo "Editing f128_mul test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_mul_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_mul_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_mul_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_mul_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_mul_rnm.tv
echo "Editing f16_div test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_div_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_div_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_div_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_div_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_div_rnm.tv
echo "Editing f32_div test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_div_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_div_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_div_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_div_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_div_rnm.tv
echo "Editing f64_div test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_div_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_div_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_div_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_div_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_div_rnm.tv
echo "Editing f128_div test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_div_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_div_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_div_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_div_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_div_rnm.tv
echo "Editing f16_sqrt test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rnm.tv
echo "Editing f32_sqrt test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rnm.tv
echo "Editing f64_sqrt test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rnm.tv
echo "Editing f128_sqrt test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rnm.tv
echo "Editing f16_eq test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_eq_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_eq_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_eq_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_eq_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_eq_rnm.tv
echo "Editing f32_eq test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_eq_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_eq_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_eq_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_eq_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_eq_rnm.tv
echo "Editing f64_eq test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_eq_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_eq_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_eq_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_eq_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_eq_rnm.tv
echo "Editing f128_eq test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_eq_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_eq_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_eq_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_eq_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_eq_rnm.tv
echo "Editing f16_le test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_le_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_le_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_le_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_le_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_le_rnm.tv
echo "Editing f32_le test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_le_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_le_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_le_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_le_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_le_rnm.tv
echo "Editing f64_le test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_le_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_le_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_le_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_le_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_le_rnm.tv
echo "Editing f128_le test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_le_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_le_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_le_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_le_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_le_rnm.tv
echo "Editing f16_lt test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_lt_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_lt_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_lt_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_lt_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_lt_rnm.tv
echo "Editing f32_lt test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_lt_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_lt_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_lt_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_lt_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_lt_rnm.tv
echo "Editing f64_lt test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_lt_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_lt_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_lt_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_lt_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_lt_rnm.tv
echo "Editing f128_lt test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_lt_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_lt_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_lt_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_lt_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_lt_rnm.tv
echo "Editing f16_mulAdd test vectors"
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rne.tv
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rz.tv
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_ru.tv
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rd.tv
sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rnm.tv
echo "Editing f32_mulAdd test vectors"
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rne.tv
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rz.tv
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_ru.tv
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rd.tv
sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rnm.tv
echo "Editing f64_mulAdd test vectors"
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rne.tv
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rz.tv
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_ru.tv
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rd.tv
sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rnm.tv
echo "Editing f128_mulAdd test vectors"
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rne.tv
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rz.tv
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_ru.tv
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rd.tv
sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rnm.tv

81
tests/fp/vectors/Makefile Executable file
View File

@ -0,0 +1,81 @@
.DELETE_ON_ERROR:
SHELL := /bin/bash
TESTFLOAT_DIR := ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC
TESTFLOAT_GEN_CMD := ${TESTFLOAT_DIR}/testfloat_gen -tininessafter -level
# List of testvectors to generate. Each rounding mode will be generated for each test.
convert := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \
ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \
i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \
i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \
f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \
f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64 \
f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \
f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \
f16_to_f32 f16_to_f64 f16_to_f128 \
f32_to_f16 f32_to_f64 f32_to_f128 \
f64_to_f16 f64_to_f32 f64_to_f128 \
f128_to_f16 f128_to_f32 f128_to_f64
add := f16_add f32_add f64_add f128_add
sub := f16_sub f32_sub f64_sub f128_sub
mul := f16_mul f32_mul f64_mul f128_mul
div := f16_div f32_div f64_div f128_div
sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt
eq := f16_eq f32_eq f64_eq f128_eq
le := f16_le f32_le f64_le f128_le
lt := f16_lt f32_lt f64_lt f128_lt
mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd
tests := $(convert) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd)
.PHONY: all rne rz ru rd rnm clean
all: rne rz ru rd rnm
# Generate test vectors for each rounding mode
rne: $(addsuffix _rne.tv, $(tests))
rz: $(addsuffix _rz.tv, $(tests))
ru: $(addsuffix _ru.tv, $(tests))
rd: $(addsuffix _rd.tv, $(tests))
rnm: $(addsuffix _rnm.tv, $(tests))
# Rules to generate individual test vectors, broken up by rounding mode
%_rne.tv: ${TESTFLOAT_GEN}
@echo Creating $*_rne.tv vectors
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
${TESTFLOAT_GEN_CMD} $$level -rnear_even $* > $@
@sed -i 's/ /_/g' $@
%_rz.tv: ${TESTFLOAT_GEN}
@echo Creating $*_rz.tv vectors
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
${TESTFLOAT_GEN_CMD} $$level -rminMag $* > $@
@sed -i 's/ /_/g' $@
%_ru.tv: ${TESTFLOAT_GEN}
@echo Creating $*_ru.tv vectors
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
${TESTFLOAT_GEN_CMD} $$level -rmax $* > $@
@sed -i 's/ /_/g' $@
%_rd.tv: ${TESTFLOAT_GEN}
@echo Creating $*_rd.tv vectors
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
${TESTFLOAT_GEN_CMD} $$level -rmin $* > $@
@sed -i 's/ /_/g' $@
%_rnm.tv: ${TESTFLOAT_GEN}
@echo Creating $*_rnm.tv vectors
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \
${TESTFLOAT_GEN_CMD} $$level -rnear_maxMag $* > $@
@sed -i 's/ /_/g' $@
# Generate TestFloat first if necessary
${TESTFLOAT_GEN}:
$(MAKE) -C ${WALLY}/tests/fp testfloat
clean:
rm -f *.tv
rm -f sed*

0
tests/fp/case.sh → tests/fp/vectors/case.sh
View File

14
tests/riscof/Makefile
View File

@ -4,8 +4,7 @@ work_dir = ./riscof_work
work = ./work
arch_workdir = $(work)/riscv-arch-test
wally_workdir = $(work)/wally-riscv-arch-test
custom_test_dir = ../../addins/cvw-arch-verif/test
submodule_work_dir = ../../addins/cvw-arch-verif/riscof_work
nproc = $(shell nproc --ignore=1)
current_dir = $(shell pwd)
#XLEN ?= 64
@ -14,16 +13,14 @@ all: root arch32 wally32 arch32e arch64 wally64
wally-riscv-arch-test: root wally64 wally32
custom: new_test
root:
mkdir -p $(work_dir)
mkdir -p $(work)
mkdir -p $(arch_workdir)
mkdir -p $(wally_workdir)
sed 's,{0},$(current_dir),g;s,{1},32gc,g' config.ini > config32.ini
sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini
sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
sed 's,{0},$(current_dir),g;s,{1},32gc,g;s,{2},$(nproc),g' config.ini > config32.ini
sed 's,{0},$(current_dir),g;s,{1},64gc,g;s,{2},$(nproc),g' config.ini > config64.ini
sed 's,{0},$(current_dir),g;s,{1},32e,g;s,{2},$(nproc),g' config.ini > config32e.ini
arch32e:
riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
@ -53,9 +50,6 @@ wally64:
quad64:
riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/ --env=$(wally_dir)/riscv-test-suite/env
new_test:
riscof run --work-dir=$(submodule_work_dir) --config=config64.ini --suite=$(custom_test_dir)/ --env=$(wally_dir)/riscv-test-suite/env --no-browser
#wally32e:
# riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
# rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"

4
tests/riscof/config.ini
View File

@ -10,8 +10,8 @@ ispec={0}/spike/spike_rv{1}_isa.yaml
pspec={0}/spike/spike_platform.yaml
target_run=1
# Optional as mentioned in https://riscof.readthedocs.io/en/latest/inputs.html#config-ini-syntax
jobs=4
jobs={2}
[sail_cSim]
pluginpath={0}/sail_cSim
jobs=4
jobs={2}

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output
View File

@ -88,6 +88,8 @@
0000000B
000000F3
00000079
00000000

8
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S
View File

@ -178,6 +178,12 @@ test_cases:
.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
.4byte rx_data, 0x0000000B, read32_test # read rx_data
# Test phase polarity
.4byte sck_mode, 0x00000003, write32_test # set sck mode to 11
.4byte tx_data, 0x000000F3, write32_test # place f3 into tx_data
.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
.4byte rx_data, 0x000000F3, read32_test # read rx_data
# Test chip select polarity
.4byte sck_mode, 0x00000000, write32_test # reset sck polarity to active high
@ -658,4 +664,4 @@ SETUP_PLIC
.4byte 0x0, 0x0, terminate_test
.4byte 0x0, 0x0, terminate_test

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/generator.py
View File

@ -55,7 +55,7 @@ def toint(x: str):
return int(x)
def get_rm(opcode):
insns = ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','fmin','fmax',
insns = ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','flq','fsq','fmin','fmax',
'fcvt.d.s', 'fcvt.d.w','fcvt.d.wu']
insns += ['fminm', 'fmaxm']
if any([x in opcode for x in insns]):
@ -242,7 +242,7 @@ class Generator():
is_nan_box = False
is_fext = any(['F' in x or 'D' in x for x in opnode['isa']])
is_fext = any(['F' in x or 'D' in x or 'Q' in x for x in opnode['isa']])
if is_fext:
if fl>ifl:
@ -260,7 +260,7 @@ class Generator():
self.is_fext = is_fext
self.is_nan_box = is_nan_box
if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd"]:
if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd","flq","fsq"]:
self.val_vars = self.val_vars + ['ea_align']
self.template = opnode['template']
self.opnode = opnode

19
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/riscv_isac/InstructionObject.py
View File

@ -2,7 +2,7 @@ import struct
instrs_sig_mutable = ['auipc','jal','jalr']
instrs_sig_update = ['sh','sb','sw','sd','c.sw','c.sd','c.swsp','c.sdsp','fsw','fsd',\
'c.fsw','c.fsd','c.fswsp','c.fsdsp']
'fsq','c.fsw','c.fsd','c.fswsp','c.fsdsp']
instrs_no_reg_tracking = ['beq','bne','blt','bge','bltu','bgeu','fence','c.j','c.jal','c.jalr',\
'c.jr','c.beqz','c.bnez', 'c.ebreak'] + instrs_sig_update
instrs_fcsr_affected = ['fmadd.s','fmsub.s','fnmsub.s','fnmadd.s','fadd.s','fsub.s','fmul.s','fdiv.s',\
@ -11,8 +11,8 @@ instrs_fcsr_affected = ['fmadd.s','fmsub.s','fnmsub.s','fnmadd.s','fadd.s','fsub
'fcvt.s.lu', 'fmadd.d','fmsub.d','fnmsub.d','fnmadd.d','fadd.d','fsub.d',\
'fmul.d','fdiv.d','fsqrt.d','fmin.d','fmax.d','fcvt.s.d','fcvt.d.s',\
'feq.d','flt.d','fle.d','fcvt.w.d','fcvt.wu.d','fcvt.l.d','fcvt.lu.d',\
'fcvt.d.l','fcvt.d.lu']
unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','fsw','fsd',\
'fcvt.d.l','fcvt.d.lu','fadd.q','fsub.q','fmadd.q','fmsub.q','fnmsub.q','fnmadd.q']
unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','flq','fsw','fsd','fsq',\
'bgeu', 'bltu', 'sltiu', 'sltu','c.lw','c.ld','c.lwsp','c.ldsp',\
'c.sw','c.sd','c.swsp','c.sdsp','mulhu','divu','remu','divuw',\
'remuw','aes64ds','aes64dsm','aes64es','aes64esm','aes64ks2',\
@ -33,9 +33,9 @@ unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\
'xperm.n','xperm.b', 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi',\
'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig1h','sha512sig0l','sha512sig0h','fsw',\
'bclr','bext','binv','bset','minu','maxu','add.uw','sh1add.uw','sh2add.uw','sh3add.uw']
f_instrs_pref = ['fadd', 'fclass', 'fcvt', 'fdiv', 'feq', 'fld', 'fle', 'flt', 'flw', 'fmadd',\
f_instrs_pref = ['fadd', 'fclass', 'fcvt', 'fdiv', 'feq', 'fld','flq', 'fle', 'flt', 'flw', 'fmadd',\
'fmax', 'fmin', 'fmsub', 'fmul', 'fmv', 'fnmadd', 'fnmsub', 'fsd', 'fsgnj', 'fsqrt',\
'fsub', 'fsw']
'fsub', 'fsw','fsq']
instr_var_evaluator_funcs = {} # dictionary for holding registered evaluator funcs
@ -146,6 +146,8 @@ class instructionObject():
instr_vars['iflen'] = 32
elif self.instr_name.endswith(".d"):
instr_vars['iflen'] = 64
elif self.instr_name.endswith(".q"):
instr_vars['iflen'] = 128
# capture the operands
if self.rs1 is not None:
@ -179,6 +181,8 @@ class instructionObject():
ea_align = (rs1_val + imm_val) % 4
if self.instr_name in ['ld','sd','fld','fsd']:
ea_align = (rs1_val + imm_val) % 8
if self.instr_name in ['flq','fsq']:
ea_align = (rs1_val + imm_val) % 16
instr_vars.update({
'rs1_val': rs1_val,
@ -439,9 +443,12 @@ class instructionObject():
if iflen == 32:
e_sz = 8
m_sz = 23
else:
elif iflen == 64:
e_sz = 11
m_sz = 52
elif iflen == 128:
e_sz = 15
m_sz = 112
bin_val = ('{:0'+str(flen)+'b}').format(reg_val)
if flen > iflen:

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/riscv_isac/cgf_normalize.py
View File

@ -43,7 +43,7 @@ def simd_val_comb(xlen, bit_width, signed=True):
:type signed: bool
'''
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd'}
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd', 128: 'q'}
sz = fmt[bit_width]
var_num = xlen//bit_width
coverpoints = []
@ -78,7 +78,7 @@ def simd_base_val(rs, xlen, bit_width, signed=True):
:type signed: bool
'''
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd'}
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd', 128: 'q'}
sz = fmt[bit_width]
var_num = xlen//bit_width

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/riscv_isac/coverage.py
View File

@ -536,8 +536,10 @@ class archState:
if flen == 32:
self.f_rf = ['00000000']*32
else:
elif flen == 64:
self.f_rf = ['0000000000000000']*32
else:
self.f_rf = ['00000000000000000000000000000']*32
self.pc = 0
self.flen = flen

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/riscv_isac/data/rvopcodesdecoder.py
View File

@ -362,7 +362,7 @@ class disassembler():
if 'rs1' in arg:
treg = reg_type
if any([instr_name.startswith(x) for x in [
'fsw','fsd','fcvt.s','fcvt.d','fmv.w','fmv.l']]):
'fsw','fsd','fsq','fcvt.s','fcvt.d','fmv.w','fmv.l']]):
treg = 'x'
temp_instrobj.rs1 = (int(get_arg_val(arg)(mcode), 2), treg)
if 'rs2' in arg:

24
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/riscv_isac/plugins/internaldecoder.py
View File

@ -18,8 +18,8 @@ class disassembler():
0b0011011: self.rv64i_arithi_ops,
0b0111011: self.rv64i_arith_ops,
0b0101111: self.rv64_rv32_atomic_ops,
0b0000111: self.flw_fld,
0b0100111: self.fsw_fsd,
0b0000111: self.flw_fld_flq,
0b0100111: self.fsw_fsd_fsq,
0b1000011: self.fmadd,
0b1000111: self.fmsub,
0b1001011: self.fnmsub,
@ -1606,7 +1606,7 @@ class disassembler():
return instrObj
def flw_fld(self, instrObj):
def flw_fld_flq(self, instrObj):
instr = instrObj.instr
rd = ((instr & self.RD_MASK) >> 7, 'f')
rs1 = ((instr & self.RS1_MASK) >> 15, 'x')
@ -1621,10 +1621,12 @@ class disassembler():
instrObj.instr_name = 'flw'
elif funct3 == 0b011:
instrObj.instr_name = 'fld'
elif funct3 == 0b100:
instrObj.instr_name = 'flq'
return instrObj
def fsw_fsd(self, instrObj):
def fsw_fsd_fsq(self, instrObj):
instr = instrObj.instr
imm_4_0 = (instr & self.RD_MASK) >> 7
imm_11_5 = (instr >> 25) << 5
@ -1642,6 +1644,8 @@ class disassembler():
instrObj.instr_name = 'fsw'
elif funct3 == 0b011:
instrObj.instr_name = 'fsd'
elif funct3 == 0b100:
instrObj.instr_name = 'fsq'
return instrObj
@ -1766,6 +1770,14 @@ class disassembler():
instrObj.instr_name = 'fmul.d'
elif funct7 == 0b0001101:
instrObj.instr_name = 'fdiv.d'
elif funct7 == 0b0000011:
instrObj.instr_name = 'fadd.q'
elif funct7 == 0b0000111:
instrObj.instr_name = 'fsub.q'
elif funct7 == 0b0001011:
instrObj.instr_name = 'fmul.q'
elif funct7 == 0b0001111:
instrObj.instr_name = 'fdiv.q'
# fsqrt
if funct7 == 0b0101100:
@ -1776,6 +1788,10 @@ class disassembler():
instrObj.instr_name = 'fsqrt.d'
instrObj.rs2 = None
return instrObj
elif funct7 == 0b0101111:
instrObj.instr_name = 'fsqrt.q'
instrObj.rs2 = None
return instrObj
# fsgnj, fsgnjn, fsgnjx
if funct7 == 0b0010000:

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output
View File

@ -88,6 +88,8 @@
00000000
0000000B
00000000
000000F3
00000000
00000079
00000000
00000000

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S
View File

@ -180,6 +180,12 @@ test_cases:
.8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
.8byte rx_data, 0x0000000B, read32_test # read rx_data
# Test phase polarity
.8byte sck_mode, 0x00000003, write32_test # set sck mode to 11
.8byte tx_data, 0x000000F3, write32_test # place f3 into tx_data
.8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
.8byte rx_data, 0x000000F3, read32_test # read rx_data
# Test chip select polarity
.8byte sck_mode, 0x00000000, write32_test # reset sck polarity to active high
@ -660,4 +666,4 @@ SETUP_PLIC
.8byte 0x0, 0x0, terminate_test
.8byte 0x0, 0x0, terminate_test