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Replaced double | and & with single. We were having issues with these verilator giving a warning about the parameter widths not matching. However the warning is not occuring anymore.

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Rose Thompson 2024-11-13 00:02:51 -06:00
parent 8993432928
commit 2fe73f8174
1 changed files with 1 additions and 10 deletions
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11
testbench/common/loggers.sv
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@ -46,7 +46,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
// performance counter logging
logic BeginSample;
logic StartSample, EndSample;
if((PrintHPMCounters || BPRED_LOGGER) && P.ZICNTR_SUPPORTED) begin : HPMCSample
if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample
integer HPMCindex;
logic StartSampleFirst;
logic StartSampleDelayed, BeginDelayed;
@ -94,15 +94,6 @@ module loggers import cvw::*; #(parameter cvw_t P,
EndSampleFirst = '0;
end
// this code needs to be with embench and coremark but not the else condition
/* -----\/----- EXCLUDED -----\/-----
if (TEST == "embench" | TEST == "coremark") begin
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
end else begin
assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
end
-----/\----- EXCLUDED -----/\----- */
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
always_comb
if (TEST == "embench" | TEST == "coremark") begin