Xavi/cvw
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645 Commits

Author SHA1 Message Date
David Harris
1b39481a16 TLB mux and swizzling cleanup 2021-07-04 12:53:52 -04:00
David Harris
735f3b4217 Replaced generates with arrays in TLB 2021-07-04 12:32:27 -04:00
David Harris
67e191c6f3 Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
David Harris
ccd9c05303 Switched to array notation for pmpchecker 2021-07-04 10:51:56 -04:00
David Harris
accbebfa6f Commented out some unused modules 2021-07-04 01:40:27 -04:00
David Harris
e90c532258 Merge conflict on linux-waves.do 2021-07-04 01:22:10 -04:00
David Harris
9645b023c9 Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
Ross Thompson
9f16d08d0d removed mmustall and finished port annotations on ptw and lsuArb. 2021-07-03 16:06:09 -05:00
Ross Thompson
043f1e10c5 Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser. 2021-07-03 15:51:25 -05:00
Ben Bracker
d8facacef6 src/cache/ICacheCntrl.sv 2021-07-03 11:24:41 -05:00
Ben Bracker
eff5a1b90f fix ICache indenting 2021-07-03 11:11:07 -05:00
David Harris
1fa4abf7b6 Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker 2021-07-03 03:29:33 -04:00
David Harris
d44916dacf Cleaned up PMA/PMP checker unused code 2021-07-03 02:25:31 -04:00
David Harris
0bd18ff662 Fixed PMPCFG read faults 2021-07-02 17:08:13 -04:00
Ross Thompson
cf688bd3f6 Fixed up the physical address generation for 64 bit page table walker. 2021-07-02 15:49:32 -05:00
Ross Thompson
8e3149517a Fixed up the bit widths on the page table walker for rv32. 2021-07-02 15:45:05 -05:00
Ross Thompson
7b3716c281 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-02 13:56:49 -05:00
Katherine Parry
20d6e57aa5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-02 12:56:53 -04:00
Katherine Parry
308c9ccaac FPU update - missing files 2021-07-02 12:53:05 -04:00
Ross Thompson
dbd33465e1 Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
David Harris
5b6ebd7935 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-02 12:52:20 -04:00
Katherine Parry
30ff212ca8 FPU update 2021-07-02 12:40:58 -04:00
David Harris
c85e0df1ff Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:04:13 -04:00
Ross Thompson
118dfa9cec added page table walker fault exit for icache. 2021-07-01 17:59:55 -05:00
Ross Thompson
61027f650c OMG. It's working! 2021-07-01 17:37:53 -05:00
Ross Thompson
6916784354 Fixed tab space issue. 2021-07-01 17:17:53 -05:00
Ross Thompson
2dc349ea6f Fixed the wrong virtual address write into the dtlb. 2021-07-01 16:55:16 -05:00
Teo Ene
ec21126474 Flow updated for 90nm 2021-07-01 13:32:42 -05:00
Ross Thompson
88a18496cf Got some stores working in virtual memory. 2021-07-01 12:49:09 -05:00
Ross Thompson
157b1b31bf Icache ITLB interlock fix. 2021-06-30 19:24:59 -05:00
Ross Thompson
002c32d2ad The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay. 2021-06-30 17:02:36 -05:00
Ross Thompson
9ec624702d Major rewrite of ptw to remove combo loop. 2021-06-30 16:25:03 -05:00
Ross Thompson
b2d8ba6742 The icache now correctly interlocks with the PTW on TLB miss. 2021-06-30 11:24:26 -05:00
Ross Thompson
dd84f2958e Page table walker now walks the table. 
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
 2021-06-29 22:33:57 -05:00
Katherine Parry
0c2b7a1132 FPU control signals changed and FMA works 2021-06-28 18:53:58 -04:00
Ross Thompson
bc9c944ba0 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
bbracker
17afd9e5e8 temporarily disable PMP checking for EBU accesses. 2021-06-26 07:19:51 -04:00
Ross Thompson
d80ebab941 AMO and LR/SC instructions now working correctly. 
Page table walking is not working.
 2021-06-25 15:42:07 -05:00
Ross Thompson
57a7074800 Some progress. Had to change how the page table walker got it's ready. 2021-06-25 15:07:41 -05:00
Ross Thompson
b4a788c341 Working through a combo loop. 2021-06-25 14:49:27 -05:00
Ross Thompson
d6c19e73f4 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
bbracker
34dbad967d ah merge; I checked and this does pass all of regression except lints 2021-06-25 07:37:06 -04:00
bbracker
192171826b changed SC M-to-E fowarding to W-to-E forwarding to improve critical path 2021-06-25 07:18:38 -04:00
Kip Macsai-Goren
d7e518991e Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR. 2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
ac597d78c8 Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations. 2021-06-24 19:59:29 -04:00
Katherine Parry
7e3483b283 FPU forwarding reworked pt.1 2021-06-24 18:39:18 -04:00
bbracker
2155a4e485 Revert "fixed forwarding" 
This reverts commit 86e369df52.
 2021-06-24 17:39:37 -04:00
Ross Thompson
6bab454b17 Works until pma checker breaks the simulation by reading HADDR rather than data physical address. 2021-06-24 14:42:59 -05:00
Ross Thompson
c02141697d Fixed combo loop in between the page table walker and i/dtlb. 2021-06-24 13:47:10 -05:00
Ross Thompson
aeeaf6d919 Progress. 2021-06-24 13:05:22 -05:00
bbracker
86e369df52 fixed forwarding 2021-06-24 11:20:21 -04:00
Kip Macsai-Goren
c8f80967a6 added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day. 2021-06-23 19:59:06 -04:00
Ross Thompson
286b4b5b26 Partial addition of page table walker arbiter. 2021-06-23 17:03:54 -05:00
Ross Thompson
9b8bcb8e57 Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two. 
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
 2021-06-23 16:43:22 -05:00
Katherine Parry
8eed89616c fpu clean-up 2021-06-23 16:42:40 -04:00
Ross Thompson
f74ecbb81e Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache. 2021-06-23 15:13:56 -05:00
Ross Thompson
349f6a9471 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-23 09:34:42 -05:00
David Harris
a514554eeb Reduced complexity of pmpadrdec 2021-06-23 03:03:52 -04:00
David Harris
2060a5c2f8 Reduced complexity of pmpadrdec 2021-06-23 02:31:50 -04:00
David Harris
fa51ab9f68 Refactored pmachecker to have adrdecs used in uncore 2021-06-23 01:41:00 -04:00
David Harris
6be0a3b8df renamed dmem to lsu and removed adrdec module from pmpadrdec 2021-06-22 23:03:43 -04:00
bbracker
fc851ca795 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-22 18:28:30 -04:00
bbracker
303f8e2a7f give EBU a dedicated PMA unit as just an address decoder 2021-06-22 18:28:08 -04:00
Ross Thompson
67cf2e1c90 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-22 15:47:16 -05:00
Katherine Parry
353a27f12f rv64f FLW passes imperas tests 2021-06-22 16:36:16 -04:00
Kip Macsai-Goren
7e06a3c04d Fixed mask assignment error, made usage, variables more clear 2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
2c41da0275 Continued fixing fsm to work right with svmode 2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
3e19eba20d updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop 2021-06-22 11:21:11 -04:00
Ross Thompson
f79e5eaa47 Icache now uses physical lenght bits rather than XLEN. 2021-06-21 16:41:09 -05:00
Ross Thompson
3cbe4c9bc2 Improved some names in icache. 2021-06-21 16:40:37 -05:00
David Harris
5d6dc82db2 Added Physical Address and Size to PMA Checker/MMU 2021-06-21 01:27:02 -04:00
David Harris
1ec90a5e1f Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
David Harris
d2ec04564b Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals 2021-06-20 22:59:04 -04:00
bbracker
23f479d225 remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR 2021-06-20 22:38:25 -04:00
Katherine Parry
2b67f25683 all rv64f instructions except convert, divide, square root, and FLD pass 2021-06-20 20:24:09 -04:00
bbracker
83a0a37f8e make xCOUNTEREN what buildroot expects it to be 2021-06-20 09:22:31 -04:00
Ross Thompson
70c45a5349 Revert "Icache now uses physical lenght bits rather than XLEN." 
This reverts commit 16266d978a.
 2021-06-19 08:58:34 -05:00
Ross Thompson
868ddce5f2 Revert "Improved some names in icache." 
This reverts commit a57c63aa7b.
 2021-06-19 08:58:32 -05:00
Ross Thompson
a57c63aa7b Improved some names in icache. 2021-06-18 12:22:41 -05:00
Ross Thompson
16266d978a Icache now uses physical lenght bits rather than XLEN. 2021-06-18 12:02:59 -05:00
David Harris
580ac1c4df Made MemPAdrM and related signals PA_BITS wide 2021-06-18 09:36:22 -04:00
David Harris
de221ff2d0 Changed physical addresses to PA_BITS in size in MMU and TLB 2021-06-18 09:11:31 -04:00
David Harris
df7e373c69 Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX 2021-06-18 08:13:15 -04:00
David Harris
35c74348a4 allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
336936cc39 Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
David Harris
de3a0c644b Further cleaning of PMA checker 2021-06-17 22:27:39 -04:00
David Harris
679e507cc6 Added SUPPORTED to each peripheral in each config file 2021-06-17 21:36:32 -04:00
David Harris
54b6a2dcad added inputs to pmaadrdec 2021-06-17 18:54:39 -04:00
David Harris
da8eb7749f Started simplifying PMA checker 2021-06-17 16:28:06 -04:00
bbracker
2bee4eabab added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version 2021-06-17 12:09:10 -04:00
bbracker
b65adbea63 enable TIME CSR for 32 bit mode as well 2021-06-17 11:34:16 -04:00
bbracker
5a661a7392 provide time and timeh CSRs based on CLINT's counter 2021-06-17 08:38:30 -04:00
bbracker
9bc5ddf5f2 PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable 2021-06-17 05:19:36 -04:00
bbracker
7b98e7aa2f mcause test fixes and s-mode interrupt bugfix 2021-06-16 17:37:08 -04:00
bbracker
cd00e04943 Merge remote-tracking branch 'origin/fixPrivTests' into main 2021-06-15 09:57:46 -04:00
Katherine Parry
4177f4f148 Updated FMA 2021-06-14 13:42:53 -04:00
David Harris
c6ff11c22e disabled Verilator WIDTH warnings in ICCacheCntrl 2021-06-12 19:50:06 -04:00
Ross Thompson
294f01cbd8 fixed the mtime register. 2021-06-11 13:50:13 -05:00
James E. Stine
11c88c15d5 Put repository of fpdivsqrt with RTL-based adder instead of structural implementation 2021-06-11 14:35:22 -04:00
David Harris
49b5fa3994 Reverted MIDELEG and MEDELEG to XLEN so busybear passes 2021-06-10 23:47:32 -04:00