Ross Thompson f79e5eaa47 Icache now uses physical lenght bits rather than XLEN.		2021-06-21 16:41:09 -05:00
..
cache	Icache now uses physical lenght bits rather than XLEN.	2021-06-21 16:41:09 -05:00
dmem	Added Physical Address and Size to PMA Checker/MMU	2021-06-21 01:27:02 -04:00
ebu	Made MemPAdrM and related signals PA_BITS wide	2021-06-18 09:36:22 -04:00
fpu	all rv64f instructions except convert, divide, square root, and FLD pass	2021-06-20 20:24:09 -04:00
generic	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
hazard	lint is clean	2021-06-07 14:22:54 -04:00
ieu	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
ifu	Icache now uses physical lenght bits rather than XLEN.	2021-06-21 16:41:09 -05:00
mmu	Added Physical Address and Size to PMA Checker/MMU	2021-06-21 01:27:02 -04:00
muldiv	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
privileged	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
uncore	Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals	2021-06-20 22:59:04 -04:00
wally	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00