bbracker 34dbad967d ah merge; I checked and this does pass all of regression except lints		2021-06-25 07:37:06 -04:00
..
cache	Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.	2021-06-23 15:13:56 -05:00
ebu	Revert "fixed forwarding"	2021-06-24 17:39:37 -04:00
fpu	FPU forwarding reworked pt.1	2021-06-24 18:39:18 -04:00
generic	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
hazard	FPU forwarding reworked pt.1	2021-06-24 18:39:18 -04:00
ieu	ah merge; I checked and this does pass all of regression except lints	2021-06-25 07:37:06 -04:00
ifu	Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.	2021-06-23 15:13:56 -05:00
lsu	Revert "fixed forwarding"	2021-06-24 17:39:37 -04:00
mmu	Reduced complexity of pmpadrdec	2021-06-23 03:03:52 -04:00
muldiv	Revert "fixed forwarding"	2021-06-24 17:39:37 -04:00
privileged	Revert "fixed forwarding"	2021-06-24 17:39:37 -04:00
uncore	Refactored pmachecker to have adrdecs used in uncore	2021-06-23 01:41:00 -04:00
wally	ah merge; I checked and this does pass all of regression except lints	2021-06-25 07:37:06 -04:00