cvw/wally-pipelined/src
2021-06-22 23:03:43 -04:00
..
cache Revert "Icache now uses physical lenght bits rather than XLEN." 2021-06-19 08:58:34 -05:00
ebu Made MemPAdrM and related signals PA_BITS wide 2021-06-18 09:36:22 -04:00
fpu rv64f FLW passes imperas tests 2021-06-22 16:36:16 -04:00
generic Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
hazard lint is clean 2021-06-07 14:22:54 -04:00
ieu Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
ifu Added Physical Address and Size to PMA Checker/MMU 2021-06-21 01:27:02 -04:00
mmu renamed dmem to lsu and removed adrdec module from pmpadrdec 2021-06-22 23:03:43 -04:00
muldiv Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
privileged Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
uncore give EBU a dedicated PMA unit as just an address decoder 2021-06-22 18:28:08 -04:00
wally renamed dmem to lsu and removed adrdec module from pmpadrdec 2021-06-22 23:03:43 -04:00