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378 Commits

Author SHA1 Message Date
cturek
c3fdc0ab23 Renamed signals to E and M stages, forwarded preprocessed n to fsm 2022-12-22 00:43:27 +00:00
cturek
ab71962dc0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 19:35:57 +00:00
cturek
c479b9f112 fixed normshift calculations 2022-12-21 19:35:47 +00:00
David Harris
e327d70cdc Removed unused FPU signals 2022-12-21 11:31:22 -08:00
David Harris
e7702e48b7 FPU remove unused signals 2022-12-20 14:43:30 -08:00
David Harris
67763dbeec Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-19 09:09:57 -08:00
David Harris
3172dfd6a9 Properly decode fcvtint to prevent unnecessary stalls 2022-12-19 09:09:48 -08:00
Ross Thompson
159eda85f0 Renamed FStallD to FPUStallD. 2022-12-19 09:28:45 -06:00
Alessandro Maiuolo
5a82898649 Added NumZeroE, AZeroM, and BZeroM 2022-12-18 20:02:40 -08:00
Alessandro Maiuolo
2989782fe6 fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8) 2022-12-18 19:04:36 -08:00
cturek
4b8cbd9fa0 Added integer support for initC 2022-12-16 19:02:11 +00:00
cturek
06c58f310d Added mux for integer special case, renamed signals to match pipelined stage 2022-12-16 18:43:49 +00:00
David Harris
7989f449ad Disabled starting FPU divider when IDIV_ON_FPU = 0 2022-12-16 06:35:29 -08:00
cturek
d7571bb9b1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-16 03:41:39 +00:00
David Harris
4365c99b52 Refactored stalls and flushes, including FDIV flush with FlushE 2022-12-15 10:56:18 -08:00
David Harris
5f637ef4a7 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
cturek
8829e627eb Fixed BZero and initU/initUM muxes 2022-12-14 16:44:46 +00:00
cturek
f57211bb49 Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs 2022-12-10 21:56:35 +00:00
Ross Thompson
de99663b97 Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." 
This reverts commit 70b89e5214.
 2022-12-04 00:01:58 +00:00
cturek
70b89e5214 Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider. 2022-12-02 21:44:29 +00:00
cturek
1f32603c30 Added flops to preproc 2022-12-02 20:31:08 +00:00
David Harris
9395414df3 Renamed FPUStallD to FCvtIntStallD 2022-12-02 11:55:23 -08:00
David Harris
d64cd715f9 Renamed DivStartE to IFDivStartE 2022-12-02 11:30:49 -08:00
David Harris
9c1b7e53e4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
cturek
7140642c93 Almost done with Int division 2022-11-22 22:22:59 +00:00
David Harris
bc3b783543 comment cleanup 2022-11-16 10:23:20 -08:00
David Harris
ddba68605e Renamed DivBusy to FDivBusyE in FPU 2022-11-16 10:13:27 -08:00
David Harris
e008d663f4 Moved DivStartE to fdivsqrtfsm 2022-11-16 10:00:07 -08:00
cturek
6fe35ee0e3 Attempt to fix FPGA synth errors 2022-11-15 20:34:28 +00:00
cturek
1c49d4a1c2 Fixed lint errors in postprocessing 2022-11-15 20:31:23 +00:00
cturek
0b2c8b9d46 Added majority of combinational logic 2022-11-14 00:06:38 +00:00
cturek
74f58b5d89 Added Quotient/Remainder calcs to normal termination 2022-11-13 23:44:34 +00:00
cturek
b3bfdbad18 Added flops for n and m, added B=0 signal 2022-11-13 23:02:43 +00:00
cturek
9c70ab917c Added A<B signal to fdivsqrt, started postprocessing merge 2022-11-13 22:40:26 +00:00
David Harris
0ce3cc393a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-13 04:23:26 -08:00
David Harris
0502b8ea4d Comments about division hazards 2022-11-13 04:17:37 -08:00
cturek
ff410cd849 Added integer step counter to fsm 2022-11-11 00:23:25 +00:00
cturek
e7c25f9562 Fixed asign and bsign 2022-11-09 18:41:26 +00:00
cturek
b137a95a35 propagated otfc swap to Rad2 and 4 qslc 2022-11-06 23:32:38 +00:00
cturek
1e927df1a0 Added conditional OTFC swap for simplified int postprocessing 2022-11-06 23:09:09 +00:00
cturek
56b7bb3590 Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv 2022-11-06 22:40:21 +00:00
cturek
ee048325cb Added n and rightshiftx 2022-11-06 22:31:48 +00:00
cturek
67f2cb0595 p calculation 2022-11-06 22:24:21 +00:00
cturek
7567f388c2 Changed lzc names, started int/fp size merge in preproc 2022-11-06 22:21:35 +00:00
cturek
333da5c945 Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench. 2022-11-06 22:08:18 +00:00
cturek
b893d9249d Added new macros for int div preprocessing, added p, n, and rightshiftx logic 2022-11-06 21:53:48 +00:00
cturek
39bf6a456e renamed remOp to RemOp 2022-11-03 22:37:25 +00:00
cturek
890b26466f Added rem/div operation to postprocessor 2022-11-02 17:49:40 +00:00
cturek
2a45787b37 Added buffered signals for int/fp 2022-10-28 21:47:24 +00:00
cturek
2ae0a9bb5d Config Cleanup 2022-10-27 22:38:56 +00:00
cturek
51fc4de0e1 small signal cleanup 2022-10-26 18:42:49 +00:00
cturek
544c142c4f abs for int inputs 2022-10-26 16:18:05 +00:00
cturek
e401d12889 Added signed division to fdivsqrt 2022-10-26 16:13:41 +00:00
cturek
94daa961b3 Started Integer Preprocessing 2022-10-25 17:48:43 +00:00
amaiuolo
a0712d1456 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-10-13 22:36:57 +00:00
amaiuolo
000117fcd4 added amaiuolo@hmc.edu 2022-10-13 22:36:52 +00:00
David Harris
6092ca757a New fdivsqrtqsel4cmp module based on comparators rather than table lookup 2022-10-09 04:47:44 -07:00
David Harris
dceb6f9034 Moved shift into divsqrt stage and cleaned up comments 2022-10-09 04:45:45 -07:00
David Harris
55e4911cf0 fdivsqrt code cleanup 2022-10-09 03:37:27 -07:00
David Harris
fc4146f409 Adding start signals for integer divider to fdivsqrt 2022-09-29 16:30:25 -07:00
cturek
c72e2e5d49 Added integer inputs and flags to divsqrt 2022-09-29 23:08:27 +00:00
David Harris
cfa83fdd98 For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc 2022-09-21 13:30:35 -07:00
David Harris
f08d5b23d5 Eliminated store after store stall when no cache; simplified divshiftcalc logic. 2022-09-21 13:02:34 -07:00
David Harris
1c8581dd6d Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest 2022-09-21 10:35:08 -07:00
David Harris
f87e15388a commented SpecialCase 2022-09-21 05:02:08 -07:00
David Harris
b21e36a788 Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc 2022-09-21 04:55:43 -07:00
David Harris
437fd52bf6 Gated sticky bit in fdiv with SpecialCase 2022-09-20 20:05:00 -07:00
David Harris
9c8edb9cb6 renamed u to udigit to avoid conflict with U 2022-09-20 19:29:23 -07:00
cturek
e8f2715a81 Fixed R4 Sqrt overshifting 2022-09-21 00:05:36 +00:00
cturek
49a1259cf9 Fixed fgen4 2022-09-20 20:00:01 +00:00
David Harris
811f498f63 renamed q to u for unified digit selection 2022-09-20 04:35:14 -07:00
David Harris
705a2bd97b Removed D2 and D2b from radix2 stage 2022-09-20 04:20:38 -07:00
David Harris
c77ec2aa9c Simplified UM initialization 2022-09-20 04:18:12 -07:00
David Harris
956011b40b fdivsqrtfgen4 comments 2022-09-20 04:13:21 -07:00
David Harris
8d1408a9d6 Moved fpu modules into subdirectories 2022-09-20 04:12:05 -07:00
David Harris
0af8151c2a Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
David Harris
5b13140078 Simplified fdivsqrtpostproc QmM logic 2022-09-20 03:30:18 -07:00
David Harris
8647de5ee4 make QmM size b+1 indpenedent of radix 2022-09-20 03:25:09 -07:00
David Harris
31c3b62774 clean up divshiftcalc 2022-09-20 03:19:50 -07:00
David Harris
7177745111 clean up divshiftcalc 2022-09-20 03:17:29 -07:00
David Harris
b48bbc4294 clean up divshiftcalc 2022-09-20 03:13:11 -07:00
David Harris
010c88816b clean up divshiftcalc 2022-09-20 03:08:25 -07:00
David Harris
712f1d8d3a Cleaning up divshiftcalc LOGNORMSHIFTSZ 2022-09-20 02:35:01 -07:00
cturek
85b3e9bfe6 Radix 4 sqrt passing first two tests 2022-09-19 21:26:32 +00:00
David Harris
1e6bd26bb6 Removed EarlyTermShift from fdiv 2022-09-19 08:44:23 -07:00
David Harris
a36747fda0 Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
David Harris
34bd82e4a3 fdivsqrtiter simplification 2022-09-19 01:08:01 -07:00
David Harris
b19c37eb0f Reduced number of cycles needed for division 2022-09-19 01:02:04 -07:00
David Harris
7826cf0bcb Cleaned up otfc4 2022-09-19 00:58:20 -07:00
David Harris
6bab8f0e3f OTFC simplification 2022-09-19 00:51:56 -07:00
David Harris
362056f53d Removed unused otfc for Q 2022-09-19 00:43:27 -07:00
David Harris
32028c437c fdiv cleanup 2022-09-19 00:32:34 -07:00
David Harris
b7b082482f Division working again for radix 2 with unified OTFC 2022-09-19 00:30:30 -07:00
David Harris
91194a9c3e Unified on-the-fly conversion working for radix 2; broke radix-4 division 2022-09-19 00:04:00 -07:00
David Harris
9fb3382ec3 Added 2 bits to C to initialize properly 2022-09-18 22:44:22 -07:00
David Harris
33933dd6b0 Added 2 bits to C to initialize properly 2022-09-18 22:42:35 -07:00
David Harris
f65d941561 Reduced number of cycles required for lower-precision sqrt 2022-09-17 09:55:34 -07:00
David Harris
54ad15d595 Starting to adust number of cycles for division/sqrt 2022-09-17 05:58:59 -07:00
cturek
f07d4b3481 Fixed j1 to align with new C reg 2022-09-16 02:15:48 +00:00
David Harris
877cc63063 FDIVSQRT cleanup 2022-09-15 09:10:57 -07:00
cturek
5b35473339 Added shift for radix 4 sqrt 2022-09-14 17:34:24 +00:00
cturek
9757d8ce3e Moved X-1 to preproc 2022-09-14 17:26:56 +00:00
cturek
8378d6b871 removed unnecessary XZero from wsmux 2022-09-14 16:59:52 +00:00
David Harris
2babf1fd7a Removed unused signals 2022-09-12 11:35:35 -07:00
David Harris
1688d544b9 Moved C to shift before rather than after using in an iteration 2022-09-08 16:05:53 -07:00
David Harris
1c3064af08 divsqrt comment cleanup 2022-09-08 15:40:42 -07:00
David Harris
e0a9b19008 CSA-based completion detection 2022-09-08 14:58:08 -07:00
David Harris
f628622ea0 Factored out aplusbeq0 unit 2022-09-07 11:36:35 -07:00
David Harris
d91b4de348 Preprocessing cleanup 2022-09-07 10:21:27 -07:00
David Harris
29f41c6792 Continued simplifying fdivsqrt postprocessing 2022-09-07 07:02:22 -07:00
David Harris
461b9d370d Continued simplifying fdivsqrt postprocessing 2022-09-07 07:00:13 -07:00
David Harris
825d3169d9 Moving postprocessing into postproc block 2022-09-07 06:42:37 -07:00
David Harris
f40c6b0ec4 fdivsqrtfsm cleanup 2022-09-07 06:32:07 -07:00
David Harris
a0abe48ad2 fdivsqrtfsm cleanup 2022-09-07 06:27:01 -07:00
David Harris
8438546d52 Fixed regression for divsqrt radix2 2022-09-07 06:12:23 -07:00
David Harris
648a3aae09 Initial radix 4 square root debuggin 2022-09-01 16:57:57 -07:00
David Harris
247ce70348 Fixed lint errors in square root and improved waveforms in testfloat 2022-09-01 15:49:13 -07:00
David Harris
8fad5073cd fdiv debug 2022-08-31 14:26:31 -07:00
David Harris
e64f41f199 Checking in radix 4 square root with qsel, fgen, softc, but not working 2022-08-31 10:54:50 -07:00
David Harris
5956fbdd62 Fixed checking termination in testfloat testbench 2022-08-30 10:55:21 -07:00
David Harris
cb54e95285 commented out lines to have divider work again 2022-08-29 13:01:32 -07:00
David Harris
7b0e43bc10 Initial FDIVSQRT simplification working 2022-08-29 12:01:09 -07:00
David Harris
16cde5f87e Simplify FSM 2022-08-29 04:32:27 -07:00
David Harris
6961e499dc Renamed special case 2022-08-29 04:29:58 -07:00
David Harris
81ec1ac858 Separated out radix 2 and radix 4 stages into different modules 2022-08-29 04:26:14 -07:00
David Harris
b4cb9a678a renamed srt to fdivsqrt 2022-08-29 04:04:05 -07:00
David Harris
8b2e368805 Only stall FPU to IEU on convert instructions with dependencies 2022-08-23 12:57:18 -07:00
David Harris
113258a0d0 Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
David Harris
746842107b Improved illegal instruction checking in FPU 2022-08-23 11:08:02 -07:00
David Harris
46f30d3dbe Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 10:14:59 -07:00
David Harris
13831aa3d3 typo in srtfsm 2022-08-23 10:14:54 -07:00
Katherine Parry
f9aa94f87b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-23 16:36:32 +00:00
Katherine Parry
72a54ef621 renamed rounding bits to L,G,R,S and fixed lint warning 2022-08-23 16:36:20 +00:00
Ross Thompson
b0606a1699 Replaced FPU data replicaiton on WriteData bus with 0 extention. 2022-08-23 10:46:03 -05:00
David Harris
34eece10b8 Finished FPU-LSU interface cleanup 2022-08-22 13:43:04 -07:00
David Harris
fffad8b314 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-22 13:28:54 -07:00
David Harris
2170203847 Simplified FPU-LSU interface to skip IEU 2022-08-22 13:28:51 -07:00
Katherine Parry
a1f0c6c598 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-22 17:16:25 +00:00
Katherine Parry
1accb92745 sqrt passes - lint warnings remain 2022-08-22 17:16:12 +00:00
David Harris
1404d1c248 moved CSA to generic 2022-08-22 08:41:23 +00:00
Katherine Parry
617dc02d01 fixed -1 issue in division 2022-08-20 00:53:45 +00:00
Katherine Parry
0f077012c3 sqrt tests in regression uncommented and pass 2022-08-07 23:38:10 +00:00
Katherine Parry
8eeca3319c radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
Katherine Parry
8f1d8669b0 fixed fsw problem and removed 2 bit shift from shift correction 2022-08-03 22:16:51 +00:00
David Harris
b13cdf79b3 FMA cleanup 2022-08-02 07:42:32 -07:00
David Harris
d3e39763b6 Moved InvA to sign block; simplified fmaexpadd coding 2022-08-02 07:34:09 -07:00
David Harris
0482bf4fc0 merged lza back into main 2022-08-01 19:45:21 -07:00
David Harris
0b95ca129c Fixed fmaadd to work with new LZA 2022-08-01 19:40:55 -07:00
David Harris
8b44037f58 Parameterized fmalza 2022-08-01 16:18:02 -07:00
David Harris
6e78b46761 Completed LZA simplificaiton 2022-08-01 16:13:16 -07:00