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378 Commits

Author SHA1 Message Date
David Harris
61230c967c simplified sign handling mux 2022-12-30 07:10:47 -08:00
David Harris
3c475455d9 Clean up sqrt preproc 2022-12-30 07:00:48 -08:00
David Harris
4fb8396867 Clean up sqrt initialization mux 2022-12-30 06:55:20 -08:00
David Harris
dba3ffe767 Reduced size of preproc right shift 2022-12-30 06:47:40 -08:00
David Harris
0e9bd5dab5 fdivsqrtpreproc shift simplification 2022-12-30 06:45:51 -08:00
David Harris
e9b314f902 fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression 2022-12-30 06:40:25 -08:00
David Harris
ef37070eee Fixed register timing failure on SpecialCaseM in fdivsqrt 2022-12-29 21:09:23 -08:00
Katherine Parry
90eb4fc1f1 minor optimizations and renaming 2022-12-29 15:54:17 -06:00
Katherine Parry
89e8df084a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-29 12:37:51 -06:00
David Harris
776f4714af Clean up names and comments in divsqrt 2022-12-29 08:02:44 -08:00
David Harris
6664cb9db4 Factored out hardware unique to RV64 and to IDIV 2022-12-29 07:36:26 -08:00
Katherine Parry
1b4fa38510 one bitt removed from inital lignment shift 2022-12-28 17:46:53 -06:00
David Harris
7780b44973 fdivsqrtfsm conditional on IDIV (fixed typo) 2022-12-27 22:16:48 -08:00
David Harris
5ee44b7405 fdivsqrtfsm conditional on IDIV 2022-12-27 22:15:45 -08:00
David Harris
db933aa7e2 fdivsqrtfsm conditional on IDIV 2022-12-27 22:14:09 -08:00
Cedar Turek
ef360f0539 idiv passing radix 2, four copies 2022-12-27 22:11:18 -08:00
David Harris
9964fc9ebe Moved IDIV in fdivsqrtfms into generate block 2022-12-27 22:04:50 -08:00
David Harris
a832605658 Moved IDIV for postproc into generate block 2022-12-27 22:02:14 -08:00
David Harris
d59878a886 Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc 2022-12-27 21:53:00 -08:00
Cedar Turek
a559abe554 Fixed cycles for multiple iterations. 2-copies radix 2 passing regression. 2022-12-27 21:34:27 -08:00
David Harris
6cf73cdaee Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M 2022-12-27 21:24:38 -08:00
David Harris
c08811357c Renamed muldiv to mdu 2022-12-27 19:57:10 -08:00
David Harris
dfc0b5d1ad Removed MDUE from unnecessary places in fdivsqrt 2022-12-27 10:42:40 -08:00
David Harris
4850d058b2 fdiv typo 2022-12-27 10:30:42 -08:00
David Harris
acc9498ae2 Made SqrtE only true on square root so gating with ~MDUE can be removed) 2022-12-27 10:27:07 -08:00
David Harris
e34b8139af Check for non-negative W in int sign handling 2022-12-27 06:35:17 -08:00
Cedar Turek
f48b7d7ef9 fpu idiv working on all configs with 1 copy of radix 2! 2022-12-26 23:18:28 -08:00
Cedar Turek
0b14aa852d fpu passing idiv tests on rv32gc 1 copy of radix 2! 2022-12-26 21:47:56 -08:00
Cedar Turek
bebaf08bed took out otfc swap. updated postprocessing quotient/remainder logic for int div. 2022-12-26 21:03:56 -08:00
David Harris
c326a274ac Fixed early termination for square root 2022-12-26 08:54:57 -08:00
David Harris
2de66e9eef Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
David Harris
a7204c9012 Removed unused DivSE from FPU 2022-12-26 07:29:19 -08:00
cturek
cc6f219bdd Added A Sign register. Fixed postprocessing logic for postinc and rem calculation. 2022-12-24 06:46:52 +00:00
Ross Thompson
6e9d1eb180 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-23 19:51:23 -06:00
Katherine Parry
4b50ffac91 reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
Ross Thompson
fe9361de34 Removed XEnE, YEnE, and ZEnE from forward logic. 
Cleanup comments.
 2022-12-23 14:27:03 -06:00
Ross Thompson
af9afafdae Cleanup floating point hazard logic. 2022-12-23 14:21:47 -06:00
Ross Thompson
b4c7998ded DON'T USE. First commit in attempt to move fpustall detection into the decode stage. 2022-12-23 12:47:18 -06:00
Ross Thompson
f6f66cb79e Removed ZForwardEnE and replaced with ZEnE. 
Similar for YForwardEnE.
 2022-12-23 12:27:51 -06:00
David Harris
f038494760 Commented out fdiv early termination - broke fsqrt test 2022-12-23 00:58:55 -08:00
David Harris
e061bacc9d Fixed early termination on fdivsqrt 2022-12-23 00:53:55 -08:00
David Harris
9e21358d75 Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
David Harris
0a7ed944a5 Revert to 98b824 2022-12-22 23:58:14 -08:00
David Harris
56312cd0a6 Clean up unused FPU signals 2022-12-22 23:53:09 -08:00
David Harris
4d509f94ec FDIV merge 2022-12-22 23:03:03 -08:00
David Harris
2d72bed1f4 Removed unused signals in FPU and CSR 2022-12-22 22:59:05 -08:00
cturek
ccbad67497 Added negative-result int diviison support in U and UM registers. 13 tests pass! 2022-12-22 16:25:37 +00:00
cturek
1b7ed72ece Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00
cturek
80ca75e216 Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc. 2022-12-22 05:44:55 +00:00
cturek
0b4d81bd4a worked out some bugs with int div cycles 2022-12-22 02:22:01 +00:00
cturek
c3fdc0ab23 Renamed signals to E and M stages, forwarded preprocessed n to fsm 2022-12-22 00:43:27 +00:00
cturek
ab71962dc0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 19:35:57 +00:00
cturek
c479b9f112 fixed normshift calculations 2022-12-21 19:35:47 +00:00
David Harris
e327d70cdc Removed unused FPU signals 2022-12-21 11:31:22 -08:00
David Harris
e7702e48b7 FPU remove unused signals 2022-12-20 14:43:30 -08:00
David Harris
67763dbeec Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-19 09:09:57 -08:00
David Harris
3172dfd6a9 Properly decode fcvtint to prevent unnecessary stalls 2022-12-19 09:09:48 -08:00
Ross Thompson
159eda85f0 Renamed FStallD to FPUStallD. 2022-12-19 09:28:45 -06:00
Alessandro Maiuolo
5a82898649 Added NumZeroE, AZeroM, and BZeroM 2022-12-18 20:02:40 -08:00
Alessandro Maiuolo
2989782fe6 fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8) 2022-12-18 19:04:36 -08:00
cturek
4b8cbd9fa0 Added integer support for initC 2022-12-16 19:02:11 +00:00
cturek
06c58f310d Added mux for integer special case, renamed signals to match pipelined stage 2022-12-16 18:43:49 +00:00
David Harris
7989f449ad Disabled starting FPU divider when IDIV_ON_FPU = 0 2022-12-16 06:35:29 -08:00
cturek
d7571bb9b1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-16 03:41:39 +00:00
David Harris
4365c99b52 Refactored stalls and flushes, including FDIV flush with FlushE 2022-12-15 10:56:18 -08:00
David Harris
5f637ef4a7 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
cturek
8829e627eb Fixed BZero and initU/initUM muxes 2022-12-14 16:44:46 +00:00
cturek
f57211bb49 Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs 2022-12-10 21:56:35 +00:00
Ross Thompson
de99663b97 Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." 
This reverts commit 70b89e5214.
 2022-12-04 00:01:58 +00:00
cturek
70b89e5214 Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider. 2022-12-02 21:44:29 +00:00
cturek
1f32603c30 Added flops to preproc 2022-12-02 20:31:08 +00:00
David Harris
9395414df3 Renamed FPUStallD to FCvtIntStallD 2022-12-02 11:55:23 -08:00
David Harris
d64cd715f9 Renamed DivStartE to IFDivStartE 2022-12-02 11:30:49 -08:00
David Harris
9c1b7e53e4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
cturek
7140642c93 Almost done with Int division 2022-11-22 22:22:59 +00:00
David Harris
bc3b783543 comment cleanup 2022-11-16 10:23:20 -08:00
David Harris
ddba68605e Renamed DivBusy to FDivBusyE in FPU 2022-11-16 10:13:27 -08:00
David Harris
e008d663f4 Moved DivStartE to fdivsqrtfsm 2022-11-16 10:00:07 -08:00
cturek
6fe35ee0e3 Attempt to fix FPGA synth errors 2022-11-15 20:34:28 +00:00
cturek
1c49d4a1c2 Fixed lint errors in postprocessing 2022-11-15 20:31:23 +00:00
cturek
0b2c8b9d46 Added majority of combinational logic 2022-11-14 00:06:38 +00:00
cturek
74f58b5d89 Added Quotient/Remainder calcs to normal termination 2022-11-13 23:44:34 +00:00
cturek
b3bfdbad18 Added flops for n and m, added B=0 signal 2022-11-13 23:02:43 +00:00
cturek
9c70ab917c Added A<B signal to fdivsqrt, started postprocessing merge 2022-11-13 22:40:26 +00:00
David Harris
0ce3cc393a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-13 04:23:26 -08:00
David Harris
0502b8ea4d Comments about division hazards 2022-11-13 04:17:37 -08:00
cturek
ff410cd849 Added integer step counter to fsm 2022-11-11 00:23:25 +00:00
cturek
e7c25f9562 Fixed asign and bsign 2022-11-09 18:41:26 +00:00
cturek
b137a95a35 propagated otfc swap to Rad2 and 4 qslc 2022-11-06 23:32:38 +00:00
cturek
1e927df1a0 Added conditional OTFC swap for simplified int postprocessing 2022-11-06 23:09:09 +00:00
cturek
56b7bb3590 Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv 2022-11-06 22:40:21 +00:00
cturek
ee048325cb Added n and rightshiftx 2022-11-06 22:31:48 +00:00
cturek
67f2cb0595 p calculation 2022-11-06 22:24:21 +00:00
cturek
7567f388c2 Changed lzc names, started int/fp size merge in preproc 2022-11-06 22:21:35 +00:00
cturek
333da5c945 Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench. 2022-11-06 22:08:18 +00:00
cturek
b893d9249d Added new macros for int div preprocessing, added p, n, and rightshiftx logic 2022-11-06 21:53:48 +00:00
cturek
39bf6a456e renamed remOp to RemOp 2022-11-03 22:37:25 +00:00
cturek
890b26466f Added rem/div operation to postprocessor 2022-11-02 17:49:40 +00:00
cturek
2a45787b37 Added buffered signals for int/fp 2022-10-28 21:47:24 +00:00
cturek
2ae0a9bb5d Config Cleanup 2022-10-27 22:38:56 +00:00