cvw/pipelined/src/fpu
2022-09-19 08:30:59 -07:00
..
cvtshiftcalc.sv Rewrote convert shift calculation with always for ease of reading 2022-07-17 16:40:58 +00:00
divshiftcalc.sv divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
fclassify.sv moved ctrl signal registers into fctrl, also a lot of code cleaning 2022-07-20 02:27:39 +00:00
fcmp.sv moved ctrl signal registers into fctrl, also a lot of code cleaning 2022-07-20 02:27:39 +00:00
fctrl.sv Only stall FPU to IEU on convert instructions with dependencies 2022-08-23 12:57:18 -07:00
fcvt.sv moved ctrl signal registers into fctrl, also a lot of code cleaning 2022-07-20 02:27:39 +00:00
fdivsqrt.sv Removed unused otfc for Q 2022-09-19 00:43:27 -07:00
fdivsqrtfsm.sv Reduced number of cycles needed for division 2022-09-19 01:02:04 -07:00
fdivsqrtiter.sv Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
fdivsqrtpostproc.sv Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
fdivsqrtpreproc.sv FDIVSQRT cleanup 2022-09-15 09:10:57 -07:00
fdivsqrtstage2.sv Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
fdivsqrtstage4.sv Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
fhazard.sv added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
flags.sv renamed rounding bits to L,G,R,S and fixed lint warning 2022-08-23 16:36:20 +00:00
fma.sv Moved InvA to sign block; simplified fmaexpadd coding 2022-08-02 07:34:09 -07:00
fmaadd.sv FMA cleanup 2022-08-02 07:42:32 -07:00
fmaalign.sv Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
fmaexpadd.sv Moved InvA to sign block; simplified fmaexpadd coding 2022-08-02 07:34:09 -07:00
fmalza.sv Parameterized fmalza 2022-08-01 16:18:02 -07:00
fmamult.sv Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
fmashiftcalc.sv fixed fsw problem and removed 2 bit shift from shift correction 2022-08-03 22:16:51 +00:00
fmasign.sv Moved InvA to sign block; simplified fmaexpadd coding 2022-08-02 07:34:09 -07:00
fpu.sv renamed srt to fdivsqrt 2022-08-29 04:04:05 -07:00
fregfile.sv paramerterized some small fma units 2022-06-01 23:34:29 +00:00
fsgninj.sv moved ctrl signal registers into fctrl, also a lot of code cleaning 2022-07-20 02:27:39 +00:00
negateintres.sv oprimized zeros and replaced complex ?: with always_comb 2022-07-19 23:44:37 +00:00
normshift.sv srt divider merged into fpu 2022-07-07 16:01:33 -07:00
otfc.sv Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
postprocess.sv renamed rounding bits to L,G,R,S and fixed lint warning 2022-08-23 16:36:20 +00:00
qsel.sv Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
resultsign.sv renamed rounding bits to L,G,R,S and fixed lint warning 2022-08-23 16:36:20 +00:00
round.sv renamed rounding bits to L,G,R,S and fixed lint warning 2022-08-23 16:36:20 +00:00
roundsign.sv divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
shiftcorrection.sv fixed fsw problem and removed 2 bit shift from shift correction 2022-08-03 22:16:51 +00:00
specialcase.sv added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
unpack.sv added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
unpackinput.sv added input enables and improved forwarding 2022-07-21 01:20:06 +00:00