cvw/pipelined/src/fpu
2022-12-27 21:53:00 -08:00
..
fdivsqrt Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc 2022-12-27 21:53:00 -08:00
fma reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
postproc Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
fclassify.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fcmp.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fctrl.sv Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M 2022-12-27 21:24:38 -08:00
fcvt.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fhazard.sv Removed XEnE, YEnE, and ZEnE from forward logic. 2022-12-23 14:27:03 -06:00
fpu.sv Removed unused DivSE from FPU 2022-12-26 07:29:19 -08:00
fregfile.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fsgninj.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
normshift.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
unpack.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
unpackinput.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00