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244 Commits

Author SHA1 Message Date
Ross Thompson
1d9b5badee Properly flush cacheLRU. 2022-12-01 17:32:58 -06:00
Ross Thompson
cb310bfb1d Removed unused port on cacheway. 2022-12-01 11:47:48 -06:00
Ross Thompson
813b2963fb More optimization. 2022-11-30 11:26:48 -06:00
Ross Thompson
da7b13ba0a Removed reset on dirty cache bits. 2022-11-30 11:04:37 -06:00
Ross Thompson
5e5cca6ae1 Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now. 2022-11-30 11:01:25 -06:00
Ross Thompson
ac3e02692b Preparing to merge dirty and tag srams. 2022-11-30 10:40:48 -06:00
Ross Thompson
8692ccbafb Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00
Ross Thompson
e3577781b0 Optimization of cacheway. 2022-11-29 18:30:47 -06:00
Ross Thompson
9e4166407b Fixed a bug with the replacement policy. It was updating the wrong set on load hits. 2022-11-29 14:51:09 -06:00
Ross Thompson
179d321683 Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled. 2022-11-29 14:09:48 -06:00
Ross Thompson
ed54959378 Renamed signals in the cache. 2022-11-29 10:52:40 -06:00
Ross Thompson
1736983557 Cleanup cacheLRU. 2022-11-22 14:59:01 -06:00
Ross Thompson
2ae7b555be File name change for cachereplacement policy to cacheLRU 2022-11-20 22:35:02 -06:00
Ross Thompson
84679c0062 Signal name changes for LRU. 2022-11-20 22:31:36 -06:00
Ross Thompson
a1f39a8186 Finally have the correct replacement policy implementation. 2022-11-17 17:36:37 -06:00
Ross Thompson
9b2236b2a0 Progress on the cache replacement policy implementation. 2022-11-16 15:35:34 -06:00
Ross Thompson
5f7b0b8a9b Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr. 2022-11-16 12:36:58 -06:00
Ross Thompson
900a326a23 Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out. 2022-11-16 11:15:34 -06:00
Ross Thompson
f03d5d3ac8 Renamed Flush to FlushStage in the cache. 2022-11-14 14:11:05 -06:00
Ross Thompson
1a00e7bbee Changed names of cache signals. 2022-11-13 21:36:12 -06:00
Ross Thompson
31d5eabd77 Renamed Word to Beat for ahbcacheinterface. 2022-11-09 17:52:50 -06:00
Ross Thompson
42c0a10d07 Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). 
FlushW prevents writting the cache, dtim, and bus state.  FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
 2022-11-07 15:50:55 -06:00
Ross Thompson
98d4929c57 Reduced complexity of logic supressing cache operations. 2022-11-01 15:23:24 -05:00
Ross Thompson
f9a04c13df comment updates. 2022-10-22 16:28:44 -05:00
Ross Thompson
e5cae3bfa0 Moving interlockfsm changes to a temporary branch. 
reduced complexity of cache mux controls.
 2022-10-19 15:08:23 -05:00
Ross Thompson
92d7be645b Reordered the eviction and fetch in cache so it follows a more logical order. 2022-10-04 17:36:07 -05:00
Ross Thompson
52e8e0f5ef Modified cache lru to not have the delayed write. 2022-10-04 15:14:58 -05:00
Ross Thompson
afc6934249 Possible fix to the bus cache interaction. 2022-09-27 11:34:33 -05:00
Ross Thompson
dfe6bdd06d Found a hidden bug in the cache to bus fsm interlock. 2022-09-26 17:41:30 -05:00
Ross Thompson
fd2a8e621a Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed. 2022-09-26 12:48:26 -05:00
Ross Thompson
dcc00ef4b3 Renamed RW signals through the caches, bus interfaces, and IFU/LSU. 
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
 2022-09-23 11:46:53 -05:00
Ross Thompson
8a6ca027c2 The valid and dirty bits match the SRAM implementation now. 2022-09-22 16:09:09 -05:00
Ross Thompson
29087812e1 Solved the sram write first / read first issue. Works correctly with read first now. 2022-09-22 14:16:26 -05:00
Ross Thompson
cdc80c1f28 Moved other SRAMs to generic/mem. 2022-09-21 12:36:03 -05:00
Ross Thompson
91fcca9d17 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
Ross Thompson
d6fa8d51d7 Modified sram1p1rw to support 3 different implementation styles. 
SRAM, Read first, and Write first.
 2022-09-21 11:26:00 -05:00
Ross Thompson
2ae62c2869 pipelining of fetch into evict AHB requests. 2022-09-13 17:51:55 -05:00
Ross Thompson
8618045bf2 Optimization. Able to remove hptw address muxes from the E stage. 2022-09-08 15:51:18 -05:00
Ross Thompson
d6d1c5d66d Moved files around. 2022-08-31 14:08:06 -05:00
Ross Thompson
68e54977fe More cleanup. 2022-08-31 11:12:38 -05:00
Ross Thompson
0b41ed63f1 More simplifications. 2022-08-31 10:45:16 -05:00
Ross Thompson
ddd9c507fe Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier. 2022-08-31 10:36:30 -05:00
Ross Thompson
6122c03e39 Removed unused old versions of the bus controllers. 2022-08-31 09:51:54 -05:00
Ross Thompson
1c248e5164 Removed old signals. 2022-08-31 09:50:39 -05:00
Ross Thompson
5b8f888e21 Maybe fixed it? 2022-08-30 18:08:34 -05:00
Ross Thompson
96793d15c0 more progress. 2022-08-30 17:32:32 -05:00
Ross Thompson
63a824cca1 More progress. 2022-08-30 15:27:19 -05:00
Ross Thompson
a532eb61ba Progress. 2022-08-30 14:17:00 -05:00
Ross Thompson
c8a5d61cbb new cache bus fsm not working but lints. 
Forgot a few files in the last commit.
 2022-08-30 10:58:07 -05:00
David Harris
af2e71046e Fixed rv32e LSU and IFU issues 2022-08-25 20:02:38 -07:00
David Harris
d7be94fab2 Cleaned up SelBusWord 2022-08-25 11:18:13 -07:00
David Harris
cd02c894df renamed BusBuffer to FetchBuffer 2022-08-25 10:44:39 -07:00
Ross Thompson
bc0edc7bdf Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
Ross Thompson
21526957cf Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
92c3cdc27d Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation. 2022-08-21 15:28:29 -05:00
Ross Thompson
96d6218078 Possible reduction of ignorerequest. 2022-08-19 18:07:44 -05:00
Ross Thompson
5301444a61 Changed signal names. 2022-08-17 16:12:04 -05:00
Ross Thompson
970a90dd72 Better name for LSUBusWriteCrit. Changed to SelLSUBusWord. 2022-08-17 16:09:20 -05:00
Ross Thompson
acd920ae2f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 22:09:11 -05:00
Ross Thompson
f7e64fcd69 Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
Ross Thompson
171cf7413b Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
Katherine Parry
de03954946 re-added FStore2 in Cache 2022-07-29 22:54:49 +00:00
Ross Thompson
f1bd2524b7 Don't use this commit yet. Untested. 2022-07-24 15:40:52 -05:00
Ross Thompson
334008630f Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested. 2022-07-24 01:20:29 -05:00
Ross Thompson
856ac24686 Removed replay from the config files. 2022-07-24 00:34:11 -05:00
Ross Thompson
458bfbf6f6 Merged evict dirty clear with flush write back. 2022-07-24 00:22:43 -05:00
Ross Thompson
5cd6c8069d signal name cleanup. 2022-07-22 23:36:27 -05:00
Ross Thompson
7d026e02f2 cache cleanup after removing replay on cpubusy. 2022-07-22 23:30:25 -05:00
Ross Thompson
706bc819e1 cache fsm cleanup after removal of replay. 2022-07-22 23:25:09 -05:00
Ross Thompson
0f586c9ed3 Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Ross Thompson
9868e685a4 Minor cleanup of cache. 2022-07-19 23:04:23 -05:00
Ross Thompson
6c8ac7851e Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction. 2022-07-19 22:42:25 -05:00
Ross Thompson
ffda64587c Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added. 2022-07-18 23:37:18 -05:00
Ross Thompson
a88543275f Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
3670c47141 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
David Harris
2bc8ff555b added comment about checking SRAM size 2022-07-10 12:48:51 +00:00
David Harris
9cb675b2e4 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00
Katherine Parry
ca4fe08fd9 renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
James Stine
c5dfefe669 Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00
David Harris
3f9e662201 Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
David Harris
96a75d7749 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 22:00:59 +00:00
Katherine Parry
08769e35ae modified wally shared 2022-07-07 21:59:43 +00:00
David Harris
2f342c430e fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
0b40f38f02 added load and store test 2022-07-07 21:48:51 +00:00
David Harris
88e3233935 Preliminary SRAM integration 2022-07-07 19:56:20 +00:00
Ross Thompson
bd46cf76a9 Fixed an issue with direct map cache's nextway logic. 
Also found a small error in the replacement policy.
 2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
50e9b6ac53 fixed concatenation syntax 2022-07-05 22:36:54 +00:00
Katherine Parry
6baded9121 added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
David Harris
f17501ed8c Removing unused signals 2022-05-12 14:36:15 +00:00
David Harris
3efbd2565a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-03 08:53:35 -07:00
David Harris
20bbe43a23 clean up sram1p1rw; still doesn't work on Modelsim 2022.1 2022-05-03 08:31:54 -07:00
David Harris
057524b840 Formatting cache.sv 2022-05-03 10:53:20 +00:00
David Harris
9e50c3440d sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera 2022-05-03 03:50:41 -07:00
David Harris
0df73d203b Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00
Ross Thompson
396f697d2f Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
0a5b500aca Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
Ross Thompson
9dce2a0679 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Ross Thompson
6e24a807f6 mild cleanup. 2022-03-11 13:05:47 -06:00