Ross Thompson 8692ccbafb Intermediate commit. Replaced flip flop dirty bit array with sram.		2022-11-30 00:08:31 -06:00
..
cache.sv	Fixed a bug with the replacement policy. It was updating the wrong set on load hits.	2022-11-29 14:51:09 -06:00
cachefsm.sv	Renamed signals in the cache.	2022-11-29 10:52:40 -06:00
cacheLRU.sv	Fixed a bug with the replacement policy. It was updating the wrong set on load hits.	2022-11-29 14:51:09 -06:00
cacheway.sv	Intermediate commit. Replaced flip flop dirty bit array with sram.	2022-11-30 00:08:31 -06:00
subcachelineread.sv	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00