Ross Thompson 179d321683 Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.		2022-11-29 14:09:48 -06:00
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cache.sv	Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.	2022-11-29 14:09:48 -06:00
cachefsm.sv	Renamed signals in the cache.	2022-11-29 10:52:40 -06:00
cacheLRU.sv	Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.	2022-11-29 14:09:48 -06:00
cacheway.sv	Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.	2022-11-29 14:09:48 -06:00
subcachelineread.sv	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00