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769 Commits

Author SHA1 Message Date
Kip Macsai-Goren
a899606c2b Removed Sail from virt mem tests due to sail not recognizing SVADU 2023-04-11 17:41:31 -07:00
Kip Macsai-Goren
19305fe60a Added sail simulation to priv tests that support it 2023-04-11 13:26:59 -07:00
Noah Limpert
748c8dc234 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-10 19:01:32 -07:00
David Harris
90c9f29beb Merge pull request #226 from SydRiley/main 
Increased coverage for the fpu by adding directed tests to toggle signals
 2023-04-09 21:52:11 -07:00
Kevin Box
59e7c9371a Create new pmp tests 
configures all pmpcfg registers in each different address range.
 2023-04-09 16:29:57 -07:00
Noah Limpert
41c79303c6 3rd attempt to resolve conflict in lsu.S file 2023-04-09 15:52:18 -07:00
Sydeny
f4caa62efc Increasing coverage for the fpu by adding directed tests to toggle signals 2023-04-09 13:33:12 -07:00
Diego Herrera Vicioso
5f9c443781 Added test coverage for floating point registers, some PMP addresses, as well as MTVAL and MCAUSE CSRs. 2023-04-08 16:40:36 -07:00
David Harris
b27199e276 Added vm64check tests to cover IMMU vm64 2023-04-07 21:14:52 -07:00
David Harris
0d2de13990 Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf 2023-04-07 21:11:01 -07:00
David Harris
bf9db11a57 Fixed priv.S to initialize stimecmp and agree with ImperasDV 2023-04-07 20:44:01 -07:00
David Harris
16eca598ba Fixed WALLY-init-lib to return correctly even from traps from compressed instructions 2023-04-07 20:24:33 -07:00
David Harris
a49f1f785e Fixed enabling machine timer interrupt 2023-04-06 22:18:33 -07:00
David Harris
8ef9891e46 vm64 tests 2023-04-06 21:42:47 -07:00
Jacob Pease
b796b1b492 Build doesn't work. AXI Crossbar has problems. 2023-04-06 16:01:58 -05:00
David Harris
02053c5dc6 Merge pull request #210 from SydRiley/main 
Starting to extend fpu conditional coverage, reformatting ifu test cases.
 2023-04-05 14:56:16 -07:00
Sydeny
9e3d78de8b Starting to extend fpu conditional coverage, reformating ifu test cases 2023-04-05 14:10:15 -07:00
David Harris
32c5a1d83e Merge pull request #205 from kbox13/my-single-change 
Increase LSU Coverage
 2023-04-05 13:16:04 -07:00
Limnanthes Serafini
590f95d353 *.out removal 2023-04-05 12:50:26 -07:00
Limnanthes Serafini
baa537c5d3 *.out removal 2023-04-05 12:50:10 -07:00
Limnanthes Serafini
ecc580a140 *.out removal 2023-04-05 12:49:57 -07:00
Kevin Box
0f13148215 Add sfence.vma 2023-04-05 10:34:30 -07:00
Kevin Box
333bb87b05 Revert "Add sfence.vma and arch64d/f tests to increase coverage in the LSU" 
This reverts commit 28a9faa265.
 2023-04-05 10:32:25 -07:00
Kevin Box
28a9faa265 Add sfence.vma and arch64d/f tests to increase coverage in the LSU 2023-04-05 10:18:41 -07:00
Limnanthes Serafini
6ad5d81980 Further comments and attribution. 2023-04-05 02:46:31 -07:00
Limnanthes Serafini
0aadbd8492 Outfiles for the failing tests. 2023-04-05 02:42:09 -07:00
Limnanthes Serafini
6f7620e7c1 CacheSim edits, tests. I/D$ logging, Lim's version 2023-04-04 21:12:35 -07:00
Noah Limpert
6bcd47db99 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-04 20:22:00 -07:00
Noah Limpert
e887341c80 Test File for Pull Request, Attempt to fill all four ways 2023-04-03 21:54:27 -07:00
David Harris
64679654ff Merged priv.S edits 2023-04-03 18:07:14 -07:00
David Harris
fecdd6d139 Merge pull request #190 from SydRiley/main 
expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions
 2023-04-03 17:48:47 -07:00
Alexa Wright
c170777d63 Merge branch 'openhwgroup:main' into main 2023-04-03 14:30:54 -07:00
David Harris
4e2d80476e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-03 06:13:16 -07:00
Sydeny
981e5bd5f6 Manual merge for fctrl.sv, fpu.S, and ifu.S files 2023-04-03 01:55:23 -07:00
Sydeny
17d41b4d52 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-03 01:54:27 -07:00
Sydney Riley
55655157ae expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions. 2023-04-02 23:51:34 -07:00
David Harris
5712b905a7 Merge pull request #177 from amaiuolo/main 
Integrated tv generation for IFdivsqrt
 2023-04-02 18:29:38 -07:00
Alexa Wright
59596cd7cc Added tests for writing and reading to HPMCOUNTERM csrs 2023-04-01 16:02:23 -07:00
David Harris
60a8a26f2e regression cleanup; unable to run buildroot coverage because of different config file 2023-03-31 09:59:38 -07:00
David Harris
fa17487d67 Merged privileged test 2023-03-31 08:37:16 -07:00
David Harris
db542543cb Coverage improvement: ieu, hazard, priv 2023-03-31 08:34:34 -07:00
David Harris
ab82bb397c Privilege test improvements 2023-03-31 08:32:02 -07:00
Marcus Mellor
219176db9b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-31 09:54:02 -05:00
Marcus Mellor
09b2cd304f Address comments in openhwgroup/cvw#180 2023-03-31 09:51:33 -05:00
Diego Herrera Vicioso
e711948369 Merge branch 'openhwgroup:main' into main 2023-03-31 00:35:02 -07:00
Marcus Mellor
d4cb1a8582 Add comments to fpu.S indicating which lines of src/fpu/fctrl.sv are covered 2023-03-30 20:01:11 -05:00
Alessandro Maiuolo
9b290669d5 integrated tv generation for IFdivsqrt 2023-03-29 20:57:26 -07:00
Kip Macsai-Goren
cfb236dd13 Merge branch 'priv-tests' of github.com:kipmacsaigoren/cvw into priv-tests 2023-03-29 16:31:35 -07:00
Kip Macsai-Goren
a7c9d3d37b ported medelg fixes to 32 bit tests. Requires a make allclean 2023-03-29 16:31:28 -07:00
kipmacsaigoren
5cc1bc97da Merge branch 'openhwgroup:main' into priv-tests 2023-03-29 15:34:47 -07:00
Sydney Riley
4bd3121364 Manual merge in the coverage64gc 2023-03-29 15:25:27 -07:00
Kip Macsai-Goren
2e151b6b08 updated tests to reflect non-writeable bits of deleg 2023-03-29 15:24:00 -07:00
Sydney Riley
20fec0177d Corrected authorship for IFU.S tests file 2023-03-29 15:20:46 -07:00
Sydney Riley
b0237eaa8b Starting IFU tests including c.fld compressed instruction 2023-03-29 15:15:47 -07:00
Noah Limpert
6acf1dadda instantiate 5 4KiB arrays, aim to thrash all 4 ways 2023-03-29 13:08:33 -07:00
Noah Limpert
1e07460d0e access of 4KiB spaced mem locations, aim to fill + evict a line of all 4 ways 2023-03-29 13:07:34 -07:00
David Harris
d059da6eca Turned on FS bit in fpu.S coverage test 2023-03-29 06:10:05 -07:00
Diego Herrera Vicioso
36d7ddf501 Added test coverage cases for writing to STVAL, SCAUSE, SEPC, and STIMECMP CSRs. 2023-03-28 22:48:17 -07:00
David Harris
3dc1c6673d Started adding fpu fctrl tests 2023-03-28 21:13:25 -07:00
David Harris
2e5c50e24a Fixed RV32 tests after PMP fix 2023-03-28 08:35:23 -07:00
David Harris
e8904411ce Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests 2023-03-28 06:58:17 -07:00
David Harris
4594dffc7f Set PMP to allow all user/supervisor accesses in WALLY-init-lib 2023-03-28 06:46:11 -07:00
David Harris
2e238c15aa CSRS privileged coverage test 2023-03-28 04:37:56 -07:00
Jacob Pease
2d0199a354 Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore 2023-03-24 17:01:27 -05:00
Kip Macsai-Goren
106ed02a7e Revert "added premilinary boundary ccrossing cases" 
This reverts commit 7870148814.
 2023-03-24 11:27:41 -07:00
Kip Macsai-Goren
758da62a9f ported fixes to 32 bit tests 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
ff59fefcc9 replaced inerrupt tests with allowed versions 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
6f15ae1225 Added cause_s_soft_from_m_interrupt 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
7870148814 added premilinary boundary ccrossing cases 2023-03-24 11:22:39 -07:00
David Harris
f1e87c5e69 Start of EBU coverage tests 2023-03-24 08:12:02 -07:00
David Harris
b674ebf7f4 100% IEU coverage 2023-03-23 17:25:27 -07:00
David Harris
4e1bf6fbe0 Improved IEU and bitmanip test coverage 2023-03-23 14:24:41 -07:00
David Harris
121d1cea62 Added csrwrites.S test case for privileged tests 2023-03-23 10:55:32 -07:00
David Harris
f4b252522e Coverage improvements 2023-03-23 09:06:05 -07:00
David Harris
ba4e0d2721 Merged bit manip 2023-03-23 06:55:29 -07:00
David Harris
610b50a693 Added new tests from class 2023-03-23 06:38:00 -07:00
Kip Macsai-Goren
c870b16c03 Merge branch 'bit-manip' of github.com:kipmacsaigoren/cvw into bit-manip 2023-03-22 14:11:58 -07:00
kipmacsaigoren
72028ab754 Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 13:25:06 -07:00
Kip Macsai-Goren
44b5e234bd Removed unused ISA string from spike YAML 2023-03-22 13:23:52 -07:00
David Harris
3b3aa942c7 Added coverage tests to regression coverage 2023-03-22 13:00:10 -07:00
David Harris
31021265b8 Makefile improvements 2023-03-22 11:17:17 -07:00
Kevin Kim
1eb96e2221 Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 10:33:15 -07:00
David Harris
4a1592ccf8 Building infrastructure for coverage directed tests 2023-03-22 04:37:13 -07:00
Kevin Kim
3f46dff23e Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-21 11:20:05 -07:00
David Harris
18cc620e7f Added badinstr test file 2023-03-21 06:57:03 -07:00
kipmacsaigoren
2337e2ae16 Merge branch 'openhwgroup:main' into bit-manip 2023-03-07 21:29:03 -08:00
Kip Macsai-Goren
db6caedfec added in the CSR name for stimecmp(h) 2023-03-04 15:53:03 -08:00
Kip Macsai-Goren
ab6b953a4b removed changes to counteren from stimecmp tests 2023-03-04 15:46:57 -08:00
Kip Macsai-Goren
ac5c53a870 Added correct causing and handling of S time interrupts to test suite. 2023-03-04 15:04:17 -08:00
Jacob Pease
a7b547008a Commented out some fat filesystem error checks. 2023-02-28 12:18:13 -06:00
Jacob Pease
b7571a349d Preliminary work on new bootloader using new SD peripheral. 
Rewrote copyflash to take advantage of the new peripheral. The new
peripheral has the neat ability to use CMD18 in the SD card
specification, allowing us to load multiple blocks in succession,
ending the chain of CMD18 commands with a CMD17.
 2023-02-25 16:32:20 -06:00
Kip Macsai-Goren
ba3bfdf68b Manual attempt to merge with upstream changes 2023-02-22 19:42:30 -08:00
Kip Macsai-Goren
0339dc5e78 added extra commands to make dut run work with spike for bit manip tests 2023-02-21 15:26:47 -08:00
Kip Macsai-Goren
d668c563f4 Merge remote-tracking branch 'upstream/main' into main 2023-02-21 14:48:41 -08:00
David Harris
99a1683f8e Debug test case updates 2023-02-21 09:33:36 -08:00
Kip Macsai-Goren
65a5b86dd8 Merge remote-tracking branch 'upstream/main' into main 2023-02-19 16:37:18 -08:00
David Harris
f0c0111ab0 Renamed section 12.3 to 8.3 in MMU test definitions 2023-02-19 05:46:46 -08:00
Kip Macsai-Goren
9c3aa55349 merge upstream synth changes 2023-02-18 14:35:19 -08:00
Kip Macsai-Goren
ea38e05773 fixed makefile for 32 bit arch tests, restored original make for all others 2023-02-17 09:57:56 -08:00
Kip Macsai-Goren
7344f3ef30 Modified arch64 tests to remove floating point and double tests from hanging make 2023-02-17 09:51:55 -08:00
Jacob Pease
45b264fa59 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-02-16 17:36:26 -06:00
David Harris
2b80004db4 Debug test case update 2023-02-15 06:42:38 -08:00
Kevin Kim
4fed8d9196 added critical rsync command to python script and builds I-ext tests 
-rsync copies the stuff from riscof_work to work/riscv-arch-test
-
 2023-02-14 10:40:29 -08:00
Kevin Kim
5fed4c2c87 updated python script to generate bash file 2023-02-11 11:08:11 -08:00
Kevin Kim
7e4fc40dc7 changed python file to use WALLY env variable 2023-02-11 00:30:56 +00:00
Kip Macsai-Goren
76593cb282 Added necessary files to make bit make and run bit manipulation tests as part of regression 2023-02-10 10:35:19 -08:00
David Harris
9a6d7bb16d Added RVTEST_CASE to testgen header 2023-02-09 18:25:24 -08:00
David Harris
8fb513ad35 Moved test generators 2023-02-09 18:24:48 -08:00
David Harris
edbf962b5f Test gen header 2023-02-09 18:14:26 -08:00
David Harris
44fef2f2a1 debug simulating, produing discrepancy 2023-02-06 16:47:56 -08:00
David Harris
4c219de13d Fixed floating point crash in debug.S 2023-02-06 15:38:57 -08:00
David Harris
5256d3a625 More progress on debug.S, but it crashes in Spike 2023-02-04 09:59:22 -08:00
David Harris
43668a3fc5 Developing debug test 2023-02-04 08:31:47 -08:00
David Harris
2c69adc5f7 Started making debug testcase 2023-02-04 08:18:55 -08:00
David Harris
80f42a8638 Renamed regression to sim 2023-02-02 14:48:23 -08:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
Jacob Pease
1952cfc9a4 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-30 14:55:22 -06:00
David Harris
4883351bd2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-28 18:18:53 -08:00
Kip Macsai-Goren
ee1bcf62ee Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts. 2023-01-28 17:29:35 -08:00
Jacob Pease
973c932ae4 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-27 15:13:29 -06:00
Jacob Pease
264f0ba0da Removed IOBUF's from sdc_controller. 2023-01-27 14:35:34 -06:00
David Harris
d8f0e3dd70 Modified testgen to not produce reference outputs 2023-01-27 07:25:40 -08:00
David Harris
cea89f27cf Removed unused WALLY test references 2023-01-27 07:25:04 -08:00
David Harris
2af94bf283 Removed unused reference files 2023-01-27 07:21:55 -08:00
David Harris
37ba3d0fcd Removed f tests from rv32e 2023-01-27 06:15:20 -08:00
David Harris
7fbbed7927 Update riscof makefile to use rv32gc config 2023-01-27 05:57:58 -08:00
David Harris
b81b5781e1 Renamed spike_rv32imc_isa.yaml to rv32gc to reflect cases tested 2023-01-27 05:56:49 -08:00
Jacob Pease
9b612fbf6c Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-23 12:41:02 -06:00
David Harris
7d8a0d9615 Refactored setup QUESTA and SNPS paths, and removed troublesome bit manipulation test cases 2023-01-23 05:00:11 -08:00
David Harris
b173112f86 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
Jacob Pease
b618518907 Fixed typos. Apparently `defube causes a weird vivado error. 2023-01-13 16:59:18 -06:00
Jacob Pease
fa087aeb30 Initial commit for the boot process. 2023-01-10 11:19:28 -06:00
Ross Thompson
97feea2f48 Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
Ross Thompson
a35fb3addd core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
Ross Thompson
f8c656f1e0 Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
Kip Macsai-Goren
964084f0b3 added fs=00 to status fp enabled test 2022-12-22 15:15:53 -08:00
Kip Macsai-Goren
d25d699800 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Kip Macsai-Goren
a37bde7452 updated trap handler alignemnts to 64 bytes in priv tests 2022-12-22 14:23:04 -08:00
David Harris
ca949f2110 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
Ross Thompson
f6393d1288 Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
c41d58bd29 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
David Harris
00ff823d84 Restored rv32d arch test after new push 2022-12-20 10:56:33 -08:00
Ross Thompson
c3b77926d5 I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
Ross Thompson
e8c1d14abb Have a basic cache test to fill all ways and sets. 2022-12-18 17:20:30 -06:00
Ross Thompson
7a352edf13 Attempted to make a cache test. 2022-12-18 17:15:08 -06:00
Ross Thompson
9d1cb9337e Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
David Harris
643a2e7cf9 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
Kip Macsai-Goren
55627f40e2 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
4c81b6fa5f added corrrect scr read out of uart to periph test 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
4ab99904a4 added all 32 bit tests to 64 bit periph tests except gpio 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
51e78d9e48 added copies of 64 bit tests to 32 bit periph and priv tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
540d6c2f41 added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Ross Thompson
fc05e27416 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
Kip Macsai-Goren
9b1765ce92 added tests for invalid address being written to satp. Not passing regression 2022-11-27 13:22:35 -08:00
Kip Macsai-Goren
21e045eb7d added potential fix to overrun error and fifo interrupt error. test passes 2022-11-06 22:01:02 -08:00
Kip Macsai-Goren
90ef371abc fixed fifo timout handling. error now in data ready interrupt 2022-11-05 13:34:24 -07:00
Kip Macsai-Goren
c06da6e6fe fixed broken instructions so make works. 2022-11-03 23:06:20 +00:00
Ross Thompson
f1eb20ef4d Updated to put dtb into the rodata segment for our linker script. 2022-11-03 17:48:20 -05:00
Ross Thompson
1d7002e5c5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-03 17:36:04 -05:00
Ross Thompson
ccce0df535 Potentially a valid zero stage boot loader based on cva6. 2022-11-03 17:35:57 -05:00
Ross Thompson
103514a8e0 More outline for uart timeout interrupt. 2022-10-28 13:53:56 -05:00
Ross Thompson
21eca47d2e Untested change to uart test for outline of how to handle rx fifo timeout. 2022-10-28 13:31:16 -05:00
Kip Macsai-Goren
6e45698b86 Added test for UART FIFO timeout. Does not pass regression 2022-10-25 05:35:56 +00:00
Ross Thompson
a59df0c77d Created one off test to replicate the floating point forwarding hazard bug. 2022-10-22 16:29:12 -05:00
Kip Macsai-Goren
c18c181fc0 fixed endianness mstatush problem, passes make, not regression 2022-10-04 17:37:39 +00:00
Kip Macsai-Goren
e603973dff added xlen and endianness test edits. xlen passes but endinanness still won't make 2022-09-26 05:03:19 +00:00
Kip Macsai-Goren
9821a50eaa added mstatus uxl, sxl bit tests (not tested in regression yet) 2022-09-18 00:11:29 +00:00
Kip Macsai-Goren
0cc7f5719c ported endianness tests to 32 bits (not tested in regression yet) 2022-09-18 00:10:29 +00:00
Kip Macsai-Goren
c5cbe43732 Fixed typos in existing endianness test 2022-09-18 00:09:52 +00:00
Kip Macsai-Goren
e6987524ab added full coverage of subword loads and stores to endianness test 2022-09-17 23:14:38 +00:00
Kip Macsai-Goren
cc7d1c8ef9 Created initial endianness tests 2022-09-16 01:06:26 +00:00
David Harris
898dbc8e74 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
4fb467ee8a Debugging plic-s test 2022-08-03 13:21:09 +00:00
David Harris
7e5b78f240 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
cab0349701 Started plic-s tests 2022-08-03 03:48:08 +00:00
David Harris
93d7d7179e Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
David Harris
429bdae1c4 Fixed UART reference output 2022-07-27 22:16:38 +00:00
David Harris
b08c87cb47 Finished UART test 2022-07-27 04:06:59 +00:00
David Harris
75a265159b Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
slmnemo
7348af7fd5 Updated reference file for UART test 2022-07-26 09:39:31 -07:00
slmnemo
a9d5805990 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-26 09:15:20 -07:00
slmnemo
5218865a7f Committing changes made to UART test 2022-07-26 09:14:40 -07:00
David Harris
2d7f4b133c More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
c6a58eb5b6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
David Harris
416f5edfe0 More riscof makefile tuning 2022-07-25 21:15:56 +00:00
David Harris
7f7b3359b0 Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings 2022-07-25 20:50:38 +00:00
slmnemo
bfced6bfe8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
ca4511b6dc Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Daniel Torres
d0aaae26fe fixed wally rv32e tests, updated regression makefile to new testflow 2022-07-22 17:09:46 -07:00
Daniel Torres
4da96c5791 fixed 32priv tests, now passing 2022-07-22 15:35:20 -07:00
Daniel Torres
24828db612 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
4198145ce2 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
141f2a40e4 UART updates and PMA fix 2022-07-22 14:49:03 -07:00
slmnemo
9cca567136 Added test comments to reference output 2022-07-22 12:35:59 -07:00
Daniel Torres
0e75142ef4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
95fdd408ee commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
slmnemo
d38369e8bf Added new PLIC and UART tests 2022-07-22 07:12:55 -07:00
slmnemo
df568fd202 Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
Daniel Torres
8dcb794bbb added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64 2022-07-21 20:58:58 -07:00
Daniel Torres
635a02cf6a made makefile more specific, just incase future additions 2022-07-21 12:50:02 -07:00
Daniel Torres
a8faddf81f removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes 2022-07-21 12:47:51 -07:00
slmnemo
37bf837d48 fixed GPIO test by adding a new function to clear PLIC interrupts 2022-07-19 08:59:16 -07:00
Daniel Torres
4883bbb952 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-18 12:13:48 -07:00
Daniel Torres
6a77ada908 added the sail change to spike to let it all run normally 2022-07-18 12:13:15 -07:00
Katherine Parry
ac2ad1d60a fixed uncommented line in makefile 2022-07-14 00:01:07 +00:00
Katherine Parry
12a54161c0 found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
18d7fee541 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
97e7e619d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
slmnemo
e190aeb14b Fixed error in gpio test 2022-07-08 02:27:16 -07:00
Katherine Parry
7771f7b3eb added load and store test 2022-07-07 21:48:51 +00:00
slmnemo
4fa4aaa7af Resolved conflicts between different gpio files 2022-07-05 18:38:52 -07:00
slmnemo
6b2125ab0e Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests. 2022-07-05 18:21:17 -07:00
David Harris
714a3fa962 Fixed typos in gpio test comments 2022-07-05 04:57:42 +00:00
David Harris
8612465756 fixed tininess detection in TestFloat examples, merged change in WALLY-TEST-LIB 2022-07-04 03:21:04 +00:00
slmnemo
0a774d9bf3 Fixed make error 2022-07-01 16:28:29 -07:00
Daniel Torres
d1eebac73f reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished 2022-06-29 12:32:30 -07:00
Daniel Torres
2ae22ac6cb added changes to testbench, tests and riscof for additional riscof compatability 2022-06-29 12:23:40 -07:00
slmnemo
f21c3114fd Added termination line to CLINT test 2022-06-27 20:16:29 -07:00
slmnemo
228028c837 Add CLINT tests from book 2022-06-27 20:09:58 -07:00
slmnemo
7a5dba4b30 will this work in git 2022-06-27 18:59:44 -07:00
slmnemo
033ec135f8 Added reset read testcodes to GPIO 2022-06-27 18:56:35 -07:00
slmnemo
cb8ae72326 Fixed error in GPIO signature 2022-06-23 14:12:28 -07:00
David Harris
db459c3380 GPIO tests 2022-06-23 21:06:11 +00:00
slmnemo
d86a65daf0 Updating new GPIO tests 2022-06-23 13:22:00 -07:00
slmnemo
33c78e2404 Fixed wally-periph, regression is now working 2022-06-23 13:08:15 -07:00
slmnemo
80a57d0469 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 02:16:26 -07:00
slmnemo
b2cea45de0 Added rudimentary GPIO test according to testplans in chapter 15 2022-06-21 02:16:21 -07:00
Katherine Parry
03d823f5d7 added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Daniel Torres
1d4c543f71 arch tests now run on spike and sail and compare signatures during build 2022-06-17 20:53:15 -07:00
Daniel Torres
0ede7c412e removed old code from makefile, simplified code in testbench 2022-06-17 15:13:38 -07:00
Daniel Torres
475220a5ff arch bug fixes and testbench changes 2022-06-17 15:07:16 -07:00
Daniel Torres
83cce676a0 added files needed for arch to build 2022-06-16 18:05:06 -07:00
Katherine Parry
5f7072bd96 postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
DTowersM
b586e3af37 added some comments to help debuggers in the future 2022-06-10 01:44:52 +00:00
DTowersM
4e5d7ec3d6 changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability 2022-06-10 00:37:53 +00:00
Katherine Parry
b6b3f04af2 added create all vectores file 2022-06-02 21:56:47 +00:00
Katherine Parry
c5bde75e30 added createallvectors 2022-06-02 21:56:05 +00:00
Katherine Parry
c264585fe8 single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Kip Macsai-Goren
c210fb6b93 Added missing DEADBEEFs to this test as well 2022-05-12 22:31:26 +00:00
Kip Macsai-Goren
553e7bfeb9 Fixed priv test reference outputs to have the right number of "DEADBEEF"s (1024) 2022-05-12 22:30:14 +00:00
David Harris
73a84f28b9 Moved some privileged tests to be simulated. 2022-05-12 04:45:41 +00:00
David Harris
c100c9893b wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
Kip Macsai-Goren
8f748c4014 clarified some trap causing functions to use zzero register rather than li [reg] 0x0. Also updated signatures' tvals 2022-05-04 23:01:23 +00:00
Kip Macsai-Goren
88173b8bb3 added explicit clears to mstatus.mie 2022-05-04 23:00:17 +00:00
Kip Macsai-Goren
6a182efe0f Updated test libraries to reflect variable name changes 2022-05-04 21:39:36 +00:00
Kip Macsai-Goren
6a372b1a1d renamed test_loop_setup to run_test_loop 2022-05-04 21:39:09 +00:00
Kip Macsai-Goren
393edc9fd8 renamed debug to extended signature 2022-05-04 21:38:37 +00:00
Kip Macsai-Goren
0f70e48b6b updated makefrag and tests.vh to reflect removed tests, new names 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
923cbc59a3 removed fp-diabled test and leftover mimpid test 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
3cab9f0234 removed instruction misaligned tests from trap tests, signatures 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
8c96672080 renamed all tests to have lower-case titles except for WALLY 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
208827502e general test cleanup of comments and old files 2022-04-29 19:55:29 +00:00
Kip Macsai-Goren
7148429f4a re-renamed status-mie-s to status-sie 2022-04-29 19:55:13 +00:00
Kip Macsai-Goren
e557e420b6 added missing SIE test 2022-04-29 19:54:29 +00:00
Kip Macsai-Goren
f50aa61994 renamed registers in test library to RISC-V ABI name rater than x2, etc.. 2022-04-29 18:52:42 +00:00
Kip Macsai-Goren
5df381e26f renamed PIE-stack tests to status-mie for clarity 2022-04-29 18:30:39 +00:00
Kip Macsai-Goren
c3ffcd0e95 removed old unused tests from wally arch tests 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
562296c677 added missing output for sret 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
0e5cc40360 added 32 bit versions of new tests. all but timeout wait pass regression 2022-04-28 18:14:07 +00:00
Kip Macsai-Goren
c4eb59c67c added missing output on final test terminating ecall 2022-04-25 19:18:38 +00:00
Kip Macsai-Goren
7e6fefb2d9 split status.fp tests into fp enabled/disabled 2022-04-25 19:16:15 +00:00
Kip Macsai-Goren
63f3e16789 added WFI and mstatus fp, tw bit tests 2022-04-25 18:21:56 +00:00
Kip Macsai-Goren
7ca56fc033 added floating point instructions to privileged tests 2022-04-25 17:47:10 +00:00
Kip Macsai-Goren
5cf75debea comment cleanup 2022-04-25 17:47:10 +00:00
Kip Macsai-Goren
b277d3cf19 Removed test cases irrelevant to this implementation, added explanatory comments. 2022-04-22 23:06:52 +00:00
Kip Macsai-Goren
3e62a8f974 Added testing for every bit field in MIE, rather than just one 2022-04-22 23:05:54 +00:00
Kip Macsai-Goren
2cc6d3ddb4 fixed timeouts on GPIO test by enabling pins as inputs as well as outputs. 2022-04-22 22:46:11 +00:00
Kip Macsai-Goren
b5b171372d added 32 bit tests to makefrag 2022-04-20 17:33:56 +00:00
Kip Macsai-Goren
43378ada56 updated 32 bit test lib to mirror 64 bit one in interrupt handling, trap stacks 2022-04-20 17:33:40 +00:00
Kip Macsai-Goren
e28c4ac680 Added 32 bit privilege tests that work but for one bug 2022-04-20 17:32:29 +00:00
Kip Macsai-Goren
7a660a58b6 Updated 32 bit PMA tests to reflect new clint rules 2022-04-20 17:31:08 +00:00
Kip Macsai-Goren
c59c5fd13d added some explanatory comments 2022-04-20 06:48:01 +00:00
Kip Macsai-Goren
72129d98d9 Added interrupt time loop support, fixed external interrupts, fixed delegated ecallhandler 2022-04-20 06:48:01 +00:00
Kip Macsai-Goren
510021af65 added working general trap tests to regression 2022-04-20 06:48:01 +00:00
David Harris
b06490a0cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 17:59:56 +00:00
David Harris
d5531e74c6 Removed extra fields from fp vectors 2022-04-18 17:59:48 +00:00
Kip Macsai-Goren
64698aa806 Added working trap test to regression, fixed hanfling of some interrupts 2022-04-18 07:22:16 +00:00
Kip Macsai-Goren
7a99066427 removed broken test from makefrag 2022-04-17 21:25:56 +00:00
Kip Macsai-Goren
1f9c987efe added new tests to makefrag and tests.vh 2022-04-17 21:00:36 +00:00
Kip Macsai-Goren
62ac6f0dbe added more comprehensive vectoring, interrupt causing and handing 2022-04-17 20:57:12 +00:00
Kip Macsai-Goren
7ea77d1038 Added the rest of the tests lited in Chapter 5 test plan 2022-04-17 20:57:12 +00:00
Ross Thompson
57358c884e commented out wally-scratch test as it hangs during compile. 2022-04-16 15:09:17 -05:00
James E. Stine
600a2c5e2f Update mkdir in run_all.sh to guarantee no errors 2022-04-14 22:23:23 -05:00
Kip Macsai-Goren
618e677406 Updated trap handler to check interrupt vectoring before handling them and to use the mscratch instead of sp for a stack. 2022-04-06 07:13:51 +00:00
Kip Macsai-Goren
4a2aacadaa Updated PMA tests to comply with all width writes and reads to CLINT 2022-04-06 07:13:51 +00:00
David Harris
ff0bddb7df Removed outdated sample testfloat calls 2022-04-04 17:23:39 +00:00
Katherine Parry
20885f4dea generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Ross Thompson
0806d1a134 Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash. 2022-04-04 10:38:37 -05:00
Kip Macsai-Goren
c40ddc4afb small bug fixes to 64 bit library 2022-04-02 19:17:34 +00:00
Kip Macsai-Goren
64afc99a02 added unfinished tests to 32 bit library 2022-04-02 19:15:07 +00:00
Kip Macsai-Goren
39c1fdb024 updated 32 bit tests to be in line with 64 bit test library 2022-04-02 19:14:12 +00:00
Kip Macsai-Goren
f7bbae8746 removed compressed instructions from privileged tests 2022-04-02 19:12:44 +00:00
bbracker
cbff9a7755 expand WALLY-PERIPH test to use SEIP on PLIC context 1 2022-03-31 18:02:06 -07:00
Kip Macsai-Goren
8cde06b886 added basic trap tests that do not pass regression yet. updated signature adresses 2022-03-25 22:57:41 +00:00
Katherine Parry
2042374102 FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
Kip Macsai-Goren
6ac9a626e2 added preliminary files for trap/priv tests. These DO NOT pass make yet because if interrrupt handling problems 2022-03-11 20:00:54 +00:00
Kip Macsai-Goren
c9110ebb40 removed compressed instructions from gcc make for privilege tests 2022-03-11 19:09:40 +00:00
Kip Macsai-Goren
cc07a3f31f Added interrupt support (not exiting correctly yet), macros for causing traps. 2022-03-11 19:09:16 +00:00
bbracker
ddae5f6518 remove linux-testgen dir because it is now completely obsolete 2022-03-05 17:26:30 -08:00
David Harris
f2bda069da Adjusted scripts to use 2022-03-04 05:09:02 +00:00
bbracker
e28ca531e0 fix peripheral test and add it to regression 2022-03-02 23:44:39 +00:00
bbracker
e994f70dab change main.config so that buildroot expects linux.config and busybox.config to be at $RISCV/buildroot 2022-03-02 17:46:33 +00:00
bbracker
4f22a55dd4 add LRSC test and add wally64a to regression 2022-03-02 07:09:37 +00:00
bbracker
e1bea211a7 fix AMO test 2022-03-02 05:41:20 +00:00
David Harris
91a593c020 Fixed march compiling privileged tests to support AMO tests. 2022-03-01 18:02:45 +00:00
bbracker
2588055644 remove old testvector-generation folder 2022-03-01 01:46:26 +00:00
bbracker
4bee3bcf27 tentatively add WALLY-AMO test to arch test infrastructure 2022-03-01 00:40:11 +00:00
bbracker
d620fb4442 deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test 2022-03-01 00:37:46 +00:00
Kip Macsai-Goren
f54ed94dbc Changed PMA tests to only allow native length accesses to CLINT 2022-02-28 19:22:44 +00:00
Kip Macsai-Goren
7be3cef076 added snippet to ignore comments in .diff files as well 2022-02-27 23:29:46 +00:00
Kip Macsai-Goren
6ed010adda added minor sections to MMU tests that had been missing, global bits still need to be checked 2022-02-27 23:28:44 +00:00
James E. Stine
3293ebc0c0 Update FP vector scripts for testing 754 2022-02-26 14:17:41 -06:00
James E. Stine
3d258af2bb Update Makefile for SoftFloat-3e 2022-02-26 14:10:27 -06:00
James E. Stine
55e70bb1ba Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-26 13:20:59 -06:00
James E. Stine
81e1c1cdc0 Update sample SoftFloat programs 2022-02-26 13:20:50 -06:00
David Harris
eda60a7691 Moved Softfloat / TestFloat 2022-02-26 19:17:32 +00:00
James E. Stine
7ef5b4344f Delete unused FP vector scripts 2022-02-26 13:02:57 -06:00
Kip Macsai-Goren
aaa880a2f0 allowed for vectored and unvectored interrupts in trap handlers 2022-02-25 23:57:45 +00:00
Kip Macsai-Goren
d90dcae1ac added support for trap handlers in in multiple pivilege modes 2022-02-25 23:57:45 +00:00
bbracker
a6047697c3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-22 04:27:50 +00:00
bbracker
6caa97bb26 change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests 2022-02-22 03:46:08 +00:00
Kip Macsai-Goren
6a569683a7 removed macro-only file. no longer used 2022-02-21 07:15:00 +00:00
Kip Macsai-Goren
1f516bb346 made sure program isn't passing the testwith a false posistive 2022-02-21 07:14:42 +00:00
Kip Macsai-Goren
d1578d8356 added scratch register tests for 64 and 32 bits 2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
c3523dfa15 Added misa test for both 32 and 64 bits 2022-02-18 19:41:50 +00:00
Kip Macsai-Goren
53f392a62f light cleanup 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
225b38e793 added high bit registers to CSR permission tests 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
6c1383e2a0 added CSR permission and minfor to 32 bit tests 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
5df0a9531f merged test macros in with 32 bit tests 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
9266bc382e light cleanup for privileged tests 2022-02-15 17:06:16 +00:00
Kip Macsai-Goren
856ef6b85a updated tests to use the combined library 2022-02-15 17:06:16 +00:00
Kip Macsai-Goren
9a05ee3308 Began to merge test-lib and test-macros into one file 2022-02-15 17:06:16 +00:00
Kip Macsai-Goren
b90477495c updated verify to only use comments with "#" 2022-02-15 17:06:16 +00:00
Ross Thompson
d1d014bf1d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:47:15 -06:00
David Harris
9ad3f26365 Restored E tests to makefrag 2022-02-08 16:41:11 +00:00
bbracker
929a9f0f1d refactor buildroot-config-src into linux folder 2022-02-08 00:26:06 +00:00
bbracker
3263f5da77 trim away unneeded linker and header files intended for non-spike machines from wally-riscv-arch-test 2022-02-07 23:59:47 +00:00
David Harris
d0c40cca7a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-07 14:43:31 +00:00
Kip Macsai-Goren
2ef5f2612f fixed verify step to work correctly with comments. clarified copy references without simulating 2022-02-06 19:48:23 +00:00
Kip Macsai-Goren
38b75e85a0 added new tests to make and testbench 2022-02-06 19:47:22 +00:00
Kip Macsai-Goren
5377dde581 clarified csr write test 2022-02-06 19:46:29 +00:00
Kip Macsai-Goren
6e3bec9aa5 added CSR permission tests 2022-02-06 19:45:58 +00:00
Kip Macsai-Goren
04197273f6 light cleanup 2022-02-06 02:05:59 +00:00
Kip Macsai-Goren
c5b6f49b2f added comments to existing MMU tests 2022-02-06 02:05:59 +00:00
Kip Macsai-Goren
52008b122a added commenting in reference outputs that aren't simulated in spike 2022-02-06 02:05:59 +00:00
Kip Macsai-Goren
69e79ccdf3 Allowed commenting in signature files 2022-02-06 02:05:59 +00:00
David Harris
0feb624bab Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
bbracker
186267e35a Remove rv32e tests from rv32i_m Makefrag so that make XLEN=32 works 2022-02-05 21:34:50 +00:00
David Harris
16b5fee795 RV32e tests 2022-02-04 14:30:36 +00:00
David Harris
3cc20bdd0d Added E tests to repo 2022-02-03 23:42:31 +00:00
David Harris
e490705865 E tests 2022-02-03 22:55:55 +00:00
David Harris
761dae72fe Config file & wally-riscv-arch-test cleanup 2022-02-02 16:35:52 +00:00
Ross Thompson
a9b4f9b1e7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-01 10:50:38 -06:00
Ross Thompson
99bb281944 Updated fpga's bootloader to reflect the changes to the gpio address change. 2022-02-01 10:43:24 -06:00
Kip Macsai-Goren
97f5878ec4 Renamed test library 2022-01-31 20:11:21 +00:00
Kip Macsai-Goren
4d8ca0d031 updated minfo test to account for no mconfigptr 2022-01-31 20:11:21 +00:00
Kip Macsai-Goren
63f4baf357 fixed CSR read-only test to have correct output 2022-01-31 20:11:21 +00:00
Kip Macsai-Goren
1077cf08b0 added machine info test that uses new test library 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
5386f1b4fa tentatively remade test lib to use macros for more flexibility 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
01d6c3a4b9 converted library to header file for RISCV test compliance 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
e3ea593ed8 updated tests to use test title instead of number encoding 2022-01-31 05:54:42 +00:00
David Harris
975c0e72c8 Set up rv32emc config 2022-01-27 14:37:58 +00:00
Ross Thompson
aa474ad588 Added generated source code for the wally riscv arch tests rv32i_m and rv64i_m. 2022-01-27 08:11:46 -06:00
David Harris
0023c4cb57 Adjusted test cases for new GPIO base address 2022-01-26 19:15:48 +00:00
David Harris
c60bb68bff Testgen working for Lab 2 2022-01-26 18:01:51 +00:00
David Harris
f90e58ff34 New testgen.py 2022-01-26 17:21:02 +00:00
kaveh Pezeshki
3314fb48c4 added qemu patches in tests/linux-testgen/qemu 2022-01-24 07:52:07 +00:00
David Harris
380e990def moved fp to tests 2022-01-14 23:05:59 +00:00
David Harris
36d49a8a74 Moved fp tests from testbench to tests/fp 2022-01-14 23:00:46 +00:00
Kip Macsai-Goren
c99456d5e7 Fixed PMA regions, Added passing PMA tests to regression 2022-01-10 22:08:26 +00:00
Kip Macsai-Goren
53f3a6dbab comment cleanup 2022-01-09 18:16:42 +00:00
Kip Macsai-Goren
9412a5ff2d updated PMA tests, everything passes except successful writes to protected regions. 2022-01-09 18:16:00 +00:00
Kip Macsai-Goren
a22dc4d163 changed test case types to lookup table instead of beq's 2022-01-09 16:56:37 +00:00
David Harris
eff9cec415 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-06 18:10:32 +00:00
David Harris
aca26de498 FPU debug and configurable logic cleanup 2022-01-06 18:10:25 +00:00
Kip Macsai-Goren
c949764a44 fixed 32 vs 64 bit copying error 2022-01-05 23:14:12 +00:00
Kip Macsai-Goren
bd977efc7b updated pma tests for simpler test lib 2022-01-05 22:10:12 +00:00
Kip Macsai-Goren
8a8f903342 updated tests to make correctly with output verification 2022-01-05 21:43:15 +00:00
Kip Macsai-Goren
706c95a383 allowed option for tests to make without spike simulation. added postverify back in for outputs 2022-01-05 21:17:54 +00:00
Kip Macsai-Goren
1db58744b0 updated pma tests to match simpler test library. They don't pass regression yet 2022-01-05 21:13:40 +00:00
Kip Macsai-Goren
46b0cb810d fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh. 2022-01-04 21:30:38 +00:00
David Harris
115287adc8 Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
David Harris
77c00e996b Started adding asynchronous TIMECLK for CLINT 2022-01-02 21:18:16 +00:00
David Harris
e084c8868f Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion 2021-12-30 17:22:18 +00:00
David Harris
da402f93cc Fixed page table entreis so WALLY-MMU-SV32, SV39, SV48 now run 2021-12-30 16:46:19 +00:00
David Harris
c3bfa53db0 Added partially working MMU tests 2021-12-29 03:14:16 +00:00
David Harris
69243f41ad Fixed imperas C tests 2021-12-26 04:45:06 +00:00
Ross Thompson
db76878581 Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card. 
mv qemu patches to tests directory.
 2021-12-19 20:11:32 -06:00
Ross Thompson
8e4eacc18e Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4 Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
bbracker
de8e2008d2 fix parseState.py to correctly take in PMPCFG 2021-11-24 16:52:51 -08:00
bbracker
13b65fa785 increase niceness of automatic checkpoint generation 2021-11-20 12:48:23 -08:00
David Harris
d243f4bcd1 Cleaning up CoreMark benchmark 2021-11-18 20:12:52 -08:00
David Harris
54fef3e2ca vert "Simplifying riscv-coremark" 
This reverts commit bdc212cf88.
 2021-11-18 18:40:13 -08:00
David Harris
bdc212cf88 Simplifying riscv-coremark 2021-11-18 17:15:40 -08:00
David Harris
b996598b37 CoreMark testing 2021-11-18 16:14:25 -08:00
David Harris
5a521e28ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
bbracker
23bd24323b get current privilege level from GDB for checkpoints 2021-11-15 14:49:00 -08:00
David Harris
f96152fa31 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
bbracker
24c5796680 genCheckpoint path bugfix 2021-11-06 15:25:10 -07:00