mirror of
https://github.com/openhwgroup/cvw
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Started plic-s tests
This commit is contained in:
David Harris
parent
7f9b601467
commit
cab0349701
@ -0,0 +1,8 @@
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0000000b # ecall for change to supervisor mode
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00000200 # read SIP with supervisor interrupt
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00000008 # check GPIO interrupt pending on intPending1
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00000003 # Claim GPIO in supervisor context
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00000000 # No interrupts pending
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00000000 # No interrupts pending
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@ -2,7 +2,7 @@
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//
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// WALLY-plic
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//
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// Author: David_Harris@hmc.edu and Nicholas Lucio <nlucio@hmc.edu>
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// Author: Nicholas Lucio <nlucio@hmc.edu>
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//
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// Created 2022-06-16
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//
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@ -121,7 +121,7 @@ test_cases:
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000001, write32_test # clear interrupt
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.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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#.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim
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.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
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@ -1,10 +1,10 @@
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///////////////////////////////////////////
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//
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// WALLY-gpio
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// WALLY-plic-s
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//
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// Author: David_Harris@hmc.edu and Nicholas Lucio <nlucio@hmc.edu>
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//
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// Created 2022-06-16
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// Created 2022-07-29
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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@ -60,6 +60,7 @@ test_cases:
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.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3
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.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10
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.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register
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.equ PLIC_INTPENDING1, (PLIC+0x001004) # intPending0 register
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.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1
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.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1
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.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode)
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@ -108,389 +109,26 @@ test_cases:
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# =========== Initialize relevant PLIC registers ===========
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.4byte PLIC_INTPRI_GPIO, 0x00000000, write32_test # set GPIO priority to zero
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.4byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to zero
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.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
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.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
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.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # set UART priority to zero
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# =========== Enter Supervisor Mode ===========
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.4byte 0x0, 0x0, goto_s_mode # Enter supervisor mode
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# =========== Test interrupt enables and priorities ===========
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.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1
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.4byte PLIC_INTEN00, 0x00000008, write32_test # enable m-mode interrupts
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.4byte PLIC_INTEN10, 0x00000008, write32_test # enable s-mode interrupts
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.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
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.4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
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# =========== Machine-Mode Priority Testing (1.T.X) ===========
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# Test 1.0.0: GPIO int lacks priority (0 = 0)
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.4byte PLIC_THRESH0, 0x00000000, write32_test # change threshold
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect no interrupt pending *** pending bug?????
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.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.0.1: GPIO int has priority (1 > 0)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # let GPIO cause interrupts
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.0.2: meip and c/c clear without interrupt pending
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
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# Test 1.1.0: GPIO lacks priority (1 = 1)
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.4byte PLIC_THRESH0, 0x00000001, write32_test # change threshold
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.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
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.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
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.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte 0x0, 0x00000800, readsip_test # read mip
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.4byte PLIC_INTPENDING1, 0x00000008, read32_test # interrupt pending for GPIO
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.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register
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.4byte PLIC_INTPENDING1, 0x00000000, read32_test # interrupt pending cleared for GPIO
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.1.1: GPIO int has priority (2 > 1)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # let GPIO cause interrupts
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.2.0: GPIO int lacks priority (2 = 2)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_THRESH0, 0x00000002, write32_test # change threshold
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
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.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.2.1: GPIO int has priority (3 > 2)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # let GPIO cause interrupts
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.3.0: GPIO int lacks priority (3 = 3)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_THRESH0, 0x00000003, write32_test # change threshold
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
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.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.3.1: GPIO int has priority (4 > 3)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # let GPIO cause interrupts
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.4.0: GPIO int lacks priority (4 = 4)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_THRESH0, 0x00000004, write32_test # change threshold
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
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.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.4.1: GPIO int has priority (5 > 4)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # let GPIO cause interrupts
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.5.0: GPIO int lacks priority (5 = 5)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_THRESH0, 0x00000005, write32_test # change threshold
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
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.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.5.1: GPIO int has priority (6 > 5)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # let GPIO cause interrupts
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.6.0: GPIO int lacks priority (6 = 6)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_THRESH0, 0x00000006, write32_test # change threshold
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
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.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.6.1: GPIO int has priority (7 > 6)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # let GPIO cause interrupts
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.4byte 0x0, 0x00000800, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3
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.4byte 0x0, 0x00000003, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# Test 1.7.0: GPIO int lacks priority (7 = 7)
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.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high
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.4byte PLIC_THRESH0, 0x00000007, write32_test # change threshold
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.4byte 0x0, 0x00000000, readmip_test # read mip
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending
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.4byte 0x0, 0x00000000, readmclaimcomplete_test # read and clear claimcomplete
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.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared
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.4byte output_val, 0x00000000, write32_test # clear output_val
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.4byte rise_ip, 0x00000000, write32_test # clear interrupt
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# # =========== UART vs GPIO priority (2.X) =========== ***
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# .4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
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# .4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
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# .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
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# .4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max
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# # Test 2.0: GPIO Priority = UART Priority
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# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
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# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
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# .4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1
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# .4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1
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# .4byte 0x0, 0x00000800, readmip_test # read mip
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# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
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# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
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# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
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# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
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# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
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# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # UART interrupt pending was cleared
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# .4byte output_val, 0x00000000, write32_test # clear output_val
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# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
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# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
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# # Test 2.1: GPIO Priority < UART Priority
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# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
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# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
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# .4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIO Priority = 2
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# .4byte PLIC_INTPRI_UART, 0x00000003, write32_test # UART Priority = 3
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# .4byte 0x0, 0x00000800, readmip_test # read mip
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# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for UART and GPIO
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# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
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# .4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt was cleared
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# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
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# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
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# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # GPIO interrupt pending was cleared
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# .4byte output_val, 0x00000000, write32_test # clear output_val
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# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
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# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
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# # Test 2.2: GPIO Priority > UART Priority
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# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
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# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
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# .4byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # GPIO Priority = 5
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# .4byte PLIC_INTPRI_UART, 0x00000004, write32_test # UART Priority = 4
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# .4byte 0x0, 0x00000800, readmip_test # read mip
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# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
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# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
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# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
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# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
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# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
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# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # UART interrupt pending was cleared
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# .4byte output_val, 0x00000000, write32_test # clear output_val
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# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
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# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
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# # Test 2.3: GPIO Priority < UART Priority (2)
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# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
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# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
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# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
|
||||
# .4byte 0x0, 0x00000800, readmip_test # read mip
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for UART and GPIO
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # UART claim/complete process
|
||||
# .4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt was cleared
|
||||
# .4byte 0x0, 0x00000800, readmip_test # expect mip to remain high
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # GPIO claim/complete process
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # GPIO interrupt pending was cleared
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # Test 2.4: Interrupts disabled (Thresh0 = 7)
|
||||
|
||||
# .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_THRESH0, 0x00000007, write32_test # Disable m-mode interrupts
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # GPIO Priority = 7
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
|
||||
# .4byte 0x0, 0x00000000, readmip_test, # read mip
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
# .4byte 0x0, 0x00000000, readmclaimcomplete_test # no interrupt pending
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # =========== SEIP tests (3.X) ===========
|
||||
|
||||
# .4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts
|
||||
# .4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts
|
||||
# .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
# .4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
||||
|
||||
# # Test 3.0: Cause machine and supervisor interrupts
|
||||
|
||||
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
|
||||
# .4byte 0x0, 0x00000A00, readmip_test # Expect high on MEIP and SEIP
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
|
||||
# .4byte 0x0, 0x00000A00, readmip_test # Still expect high on MEIP and SEIP
|
||||
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
|
||||
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # Test 3.1: Suppress machine mode interrupts
|
||||
|
||||
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIO Priority = 3
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000002, write32_test # UART Priority = 2
|
||||
# .4byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7
|
||||
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
|
||||
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
|
||||
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # GPIO interrupt was cleared
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
|
||||
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # Test 3.2: Cause SEIP with UART first
|
||||
|
||||
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7
|
||||
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
|
||||
# .4byte 0x0, 0x00000200, readmip_test # Expect high on SEIP only
|
||||
# .4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt was cleared
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
|
||||
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # Test 3.3: Low SEIP due to insufficient priority
|
||||
|
||||
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIO Priority = 2
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000003, write32_test # UART Priority = 3
|
||||
# .4byte PLIC_THRESH0, 0x00000004, write32_test # set m-mode threshold to 7
|
||||
# .4byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 7
|
||||
# .4byte 0x0, 0x00000000, readmip_test # no interrupt pending
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending
|
||||
# .4byte 0x0, 0x00000000, readmclaimcomplete_test # Expect nothing on claim/complete
|
||||
# .4byte output_val, 0x00000000, write32_test # clear output_val
|
||||
# .4byte rise_ip, 0x00000000, write32_test # clear GPIO interrupt
|
||||
# .4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt
|
||||
|
||||
# # =========== UART interrupt enable tests (4.X) ===========
|
||||
|
||||
# .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0
|
||||
# .4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0
|
||||
# .4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1
|
||||
# .4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1
|
||||
|
||||
# # Test 4.0: GPIO m-mode disabled
|
||||
|
||||
# .4byte output_val, 0x00000000, write32_test # cause rise_ip to go high
|
||||
# .4byte UART_MSR, 0x00000010, write08_test # step 1 of UART interrupt
|
||||
# .4byte UART_MSR, 0x00000012, write08_test # step 2 of UART interrupt
|
||||
# .4byte PLIC_INTEN00, 0x000000200, write32_test # GPIO m-mode interrupt disabled
|
||||
# .4byte PLIC_INTEN00, 0x000000208, write32_test # No s-mode interrupt disabled
|
||||
# .4byte 0x0, 0x00000A00, readmip_test # Expect high on MEIP from UART and SEIP from GPIO
|
||||
# .4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x00000003, readmclaimcomplete_test # Expect GPIO on claim/complete
|
||||
# .4byte 0x0, 0x00000200, readmip_test # Expect high on MEIP and SEIP from UART
|
||||
# .4byte PLIC_INTPENDING0, 0x00000200, read32_test # interrupt pending for GPIO and UART
|
||||
# .4byte 0x0, 0x0000000A, readmclaimcomplete_test # Expect UART on claim/complete
|
||||
# .4byte 0x0, 0x00000000, readmip_test # all interrupts were cleared
|
||||
# .4byte PLIC_INTPENDING0, 0x00000000, read32_test # Pending should also be clear
|
||||
|
||||
# Test 4.1: UART m-mode disabled
|
||||
|
||||
|
||||
|
||||
# Test 4.2: GPIO s-mode disabled
|
||||
|
||||
|
||||
|
||||
# Test 4.3: UART s-mode disabled
|
||||
|
||||
|
||||
|
||||
# Test 4.4: GPIO and UART s-mode disabled
|
||||
|
||||
|
||||
|
||||
# Test 4.5: GPIO and UART m-mode disabled
|
||||
|
||||
|
||||
|
||||
# Test 4.6: GPIO and UART fully disabled
|
||||
.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt
|
||||
.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier
|
||||
.4byte PLIC_INTPENDING1, 0x00000000, read32_test # no interrupts pending
|
||||
|
||||
.4byte 0x0, 0x0, terminate_test # terminate tests
|
||||
|
||||
Loading…
Reference in New Issue
Block a user