mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 10:15:19 +00:00
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
slmnemo
commit
a9d5805990
@ -1 +1 @@
|
||||
Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
|
||||
Subproject commit e5020bf7b345f8efb96c6c939de3162525b7f545
|
||||
@ -24,8 +24,10 @@ clean:
|
||||
|
||||
riscoftests:
|
||||
# Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
|
||||
make -C ../../tests/riscof/
|
||||
make -C ../../tests/riscof/ XLEN=32
|
||||
make -C ../../tests/riscof/
|
||||
# make -C ../../tests/riscof/ XLEN=32
|
||||
# make -C ../../tests/riscof/ XLEN=32 build_rv32e
|
||||
# make -C ../../tests/riscof/ XLEN=64
|
||||
|
||||
memfiles:
|
||||
make -f makefile-memfile wally-sim-files --jobs
|
||||
|
||||
@ -64,7 +64,7 @@ tc = TestCase(
|
||||
grepstr="400100000 instructions")
|
||||
configs.append(tc)
|
||||
|
||||
tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64periph", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
|
||||
tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64f", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64periph", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
|
||||
for test in tests64gc:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
@ -73,7 +73,7 @@ for test in tests64gc:
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
tests32gc = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32f", "imperas32m", "wally32a", "imperas32c", "wally32priv", "wally32periph"] #, "imperas32mmu""wally32i",
|
||||
tests32gc = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "arch32d", "imperas32i", "imperas32f", "imperas32m", "wally32a", "imperas32c", "wally32priv", "wally32periph"] #, "imperas32mmu""wally32i",
|
||||
for test in tests32gc:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
|
||||
@ -5,38 +5,39 @@ add wave -noupdate /testbench/reset
|
||||
add wave -noupdate /testbench/reset_ext
|
||||
add wave -noupdate /testbench/memfilename
|
||||
add wave -noupdate /testbench/dut/core/SATP_REGW
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/CSRWriteFencePendingDEM
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM
|
||||
add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/StoreStallD
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWriteFencePendingDEM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/StoreStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
@ -55,10 +56,10 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
|
||||
add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM
|
||||
add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM
|
||||
add wave -noupdate -group {Memory Stage} /testbench/InstrMName
|
||||
add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/PCW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||
@ -125,12 +126,12 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/if
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCF
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCE
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCM
|
||||
add wave -noupdate -group PCS /testbench/PCW
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/PCF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
|
||||
add wave -noupdate -expand -group PCS /testbench/PCW
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
|
||||
@ -223,73 +224,65 @@ add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbe
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
|
||||
@ -324,8 +317,10 @@ add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
@ -367,18 +362,8 @@ add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SU
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
|
||||
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
|
||||
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWRITE
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADY
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HTRANS
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWDATA
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress
|
||||
@ -392,41 +377,12 @@ add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/pl
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/max_priority_with_irqs
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqs_at_max_priority
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWDATA
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWRITE
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADY
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HTRANS
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HRESPGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADYGPIO
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HCLK
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HSELCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HADDR
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWRITE
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWDATA
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADY
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HTRANS
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HRESPCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADYCLINT
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HCLK
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESETn
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HSELUART
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HADDR
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWRITE
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWDATA
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADUART
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESPUART
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADYUART
|
||||
add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uart/uart/u/LSR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MCR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MSR
|
||||
@ -468,30 +424,81 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
|
||||
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
|
||||
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
|
||||
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
|
||||
add wave -noupdate -group ifu -color Gold /testbench/dut/core/ifu/bus/busdp/busfsm/BusCurrState
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAck
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusHRDATA
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUTransComplete
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
|
||||
add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusWriteData
|
||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
||||
add wave -noupdate -expand -group ifu -color Gold /testbench/dut/core/ifu/bus/busdp/busfsm/BusCurrState
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusRead
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAdr
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAck
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusHRDATA
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUTransComplete
|
||||
add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
|
||||
add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
|
||||
add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
|
||||
add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusWriteData
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetDirtyWay
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetValidWay
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/ByteMask}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/ReadData}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
||||
add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||
add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||
add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
@ -508,9 +515,14 @@ add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {D
|
||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
||||
add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/NextPTE
|
||||
add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/UpdatePTE
|
||||
add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/FinalByteMask}
|
||||
add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrFlag
|
||||
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
|
||||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/InvalidateCacheM
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 5} {0 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
WaveRestoreCursors {{Cursor 2} {989221 ns} 1} {{Cursor 3} {999815 ns} 1} {{Cursor 4} {993418 ns} 0}
|
||||
quietly wave cursor active 3
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 314
|
||||
configure wave -justifyvalue left
|
||||
@ -525,4 +537,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {208 ns}
|
||||
WaveRestoreZoom {993352 ns} {993510 ns}
|
||||
|
||||
62
pipelined/src/cache/cache.sv
vendored
62
pipelined/src/cache/cache.sv
vendored
@ -38,7 +38,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
|
||||
input logic [1:0] RW,
|
||||
input logic [1:0] Atomic,
|
||||
input logic FlushCache,
|
||||
input logic InvalidateCacheM,
|
||||
input logic InvalidateCache,
|
||||
input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits.
|
||||
input logic [`PA_BITS-1:0] PAdr, // physical address
|
||||
input logic [(`XLEN-1)/8:0] ByteMask,
|
||||
@ -79,7 +79,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
|
||||
logic ClearValid;
|
||||
logic ClearDirty;
|
||||
logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
|
||||
logic [NUMWAYS-1:0] HitWay, HitWaySaved, HitWayFinal;
|
||||
logic [NUMWAYS-1:0] HitWay;
|
||||
logic CacheHit;
|
||||
logic SetDirty;
|
||||
logic SetValid;
|
||||
@ -105,9 +105,15 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
|
||||
logic [NUMWAYS-1:0] SelectedWay;
|
||||
logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay;
|
||||
logic [1:0] CacheRW, CacheAtomic;
|
||||
logic [LINELEN-1:0] ReadDataLine;
|
||||
logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache;
|
||||
logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
|
||||
logic save, restore;
|
||||
logic SelBusBuffer;
|
||||
logic SRAMEnable;
|
||||
|
||||
localparam LOGXLENBYTES = $clog2(`XLEN/8);
|
||||
logic [2**LOGWPL-1:0] MemPAdrDecoded;
|
||||
logic [LINELEN/8-1:0] LineByteMask, DemuxedByteMask, LineByteMux;
|
||||
genvar index;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Read Path
|
||||
@ -121,31 +127,22 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
|
||||
|
||||
// Array of cache ways, along with victim, hit, dirty, and read merging logic
|
||||
cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN)
|
||||
CacheWays[NUMWAYS-1:0](.clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteMask, .FStore2,
|
||||
CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .CacheWriteData, .LineByteMask, .FStore2,
|
||||
.SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
|
||||
.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay,
|
||||
.Invalidate(InvalidateCacheM));
|
||||
.Invalidate(InvalidateCache));
|
||||
if(NUMWAYS > 1) begin:vict
|
||||
cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(
|
||||
.clk, .reset, .HitWay(HitWayFinal), .VictimWay, .RAdr, .LRUWriteEn);
|
||||
.clk, .reset, .HitWay, .VictimWay, .RAdr, .LRUWriteEn);
|
||||
end else assign VictimWay = 1'b1; // one hot.
|
||||
assign CacheHit = | HitWay;
|
||||
assign VictimDirty = | VictimDirtyWay;
|
||||
// ReadDataLineWay is a 2d array of cache line len by number of ways.
|
||||
// Need to OR together each way in a bitwise manner.
|
||||
// Final part of the AO Mux. First is the AND in the cacheway.
|
||||
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLine));
|
||||
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLineCache));
|
||||
or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
|
||||
|
||||
// Because of the sram clocked read when the ieu is stalled the read data maybe lost.
|
||||
// There are two ways to resolve. 1. We can replay the read of the sram or we can save
|
||||
// the data. Replay is eaiser but creates a longer critical path.
|
||||
// save/restore only wayhit and readdata.
|
||||
if(!`REPLAY) begin
|
||||
flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, HitWay, HitWaySaved);
|
||||
mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal);
|
||||
end else assign HitWayFinal = HitWay;
|
||||
|
||||
// like to fix this.
|
||||
if(DCACHE)
|
||||
mux2 #(LOGWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]),
|
||||
@ -153,15 +150,33 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
|
||||
.y(WordOffsetAddr));
|
||||
else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];
|
||||
|
||||
mux2 #(LINELEN) EarlyReturnBuf(ReadDataLineCache, CacheBusWriteData, SelBusBuffer, ReadDataLine);
|
||||
|
||||
subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL, LOGWPL) subcachelineread(
|
||||
.clk, .reset, .PAdr(WordOffsetAddr), .save, .restore,
|
||||
.PAdr(WordOffsetAddr),
|
||||
.ReadDataLine, .ReadDataWord);
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Write Path: Write data and address. Muxes between writes from bus and writes from CPU.
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
|
||||
.d1(CacheBusWriteData), .s(SetValid), .y(CacheWriteData));
|
||||
logic [LINELEN-1:0] FinalWriteDataDup;
|
||||
assign FinalWriteDataDup = {WORDSPERLINE{FinalWriteData}};
|
||||
|
||||
onehotdecoder #(LOGWPL) adrdec(
|
||||
.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
|
||||
for(index = 0; index < 2**LOGWPL; index++) begin
|
||||
assign DemuxedByteMask[(index+1)*(`XLEN/8)-1:index*(`XLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
|
||||
end
|
||||
// *** have to add back in fstore2
|
||||
assign LineByteMux = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1.
|
||||
assign LineByteMask = ~SetValid & ~SetDirty ? '0 : ~SetValid & SetDirty ? DemuxedByteMask : '1; // if store hit only enable the word and subword bytes, else write all bytes.
|
||||
|
||||
for(index = 0; index < LINELEN/8; index++) begin
|
||||
mux2 #(8) WriteDataMux(.d0(FinalWriteDataDup[8*index+7:8*index]),
|
||||
.d1(CacheBusWriteData[8*index+7:8*index]), .s(LineByteMux[index]), .y(CacheWriteData[8*index+7:8*index]));
|
||||
end
|
||||
//mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
|
||||
// .d1(CacheBusWriteData), .s(SetValid), .y(CacheWriteData));
|
||||
mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
|
||||
.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
|
||||
.d2({VictimTag, FlushAdr, {OFFSETLEN{1'b0}}}),
|
||||
@ -185,7 +200,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Write Path: Write Enables
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
mux3 #(NUMWAYS) selectwaymux(HitWayFinal, VictimWay, FlushWay,
|
||||
mux3 #(NUMWAYS) selectwaymux(HitWay, VictimWay, FlushWay,
|
||||
{SelFlush, SetValid}, SelectedWay);
|
||||
assign SetValidWay = SetValid ? SelectedWay : '0;
|
||||
assign ClearValidWay = ClearValid ? SelectedWay : '0;
|
||||
@ -204,7 +219,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
|
||||
.ClearValid, .ClearDirty, .SetDirty,
|
||||
.SetValid, .SelEvict, .SelFlush,
|
||||
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
|
||||
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
|
||||
.save, .restore,
|
||||
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelBusBuffer,
|
||||
.InvalidateCache,
|
||||
.SRAMEnable,
|
||||
.LRUWriteEn);
|
||||
endmodule
|
||||
|
||||
128
pipelined/src/cache/cachefsm.sv
vendored
128
pipelined/src/cache/cachefsm.sv
vendored
@ -32,50 +32,51 @@
|
||||
|
||||
module cachefsm
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic reset,
|
||||
// inputs from IEU
|
||||
input logic [1:0] CacheRW,
|
||||
input logic [1:0] CacheAtomic,
|
||||
input logic FlushCache,
|
||||
input logic FlushCache,
|
||||
input logic InvalidateCache,
|
||||
// hazard inputs
|
||||
input logic CPUBusy,
|
||||
input logic CPUBusy,
|
||||
// interlock fsm
|
||||
input logic IgnoreRequestTLB,
|
||||
input logic IgnoreRequestTrapM,
|
||||
input logic IgnoreRequestTLB,
|
||||
input logic IgnoreRequestTrapM,
|
||||
input logic TrapM,
|
||||
// Bus inputs
|
||||
input logic CacheBusAck,
|
||||
input logic CacheBusAck,
|
||||
// dcache internals
|
||||
input logic CacheHit,
|
||||
input logic VictimDirty,
|
||||
input logic FlushAdrFlag,
|
||||
input logic FlushWayFlag,
|
||||
input logic CacheHit,
|
||||
input logic VictimDirty,
|
||||
input logic FlushAdrFlag,
|
||||
input logic FlushWayFlag,
|
||||
|
||||
// hazard outputs
|
||||
output logic CacheStall,
|
||||
output logic CacheStall,
|
||||
// counter outputs
|
||||
output logic CacheMiss,
|
||||
output logic CacheAccess,
|
||||
output logic CacheMiss,
|
||||
output logic CacheAccess,
|
||||
// Bus outputs
|
||||
output logic CacheCommitted,
|
||||
output logic CacheWriteLine,
|
||||
output logic CacheFetchLine,
|
||||
output logic CacheCommitted,
|
||||
output logic CacheWriteLine,
|
||||
output logic CacheFetchLine,
|
||||
|
||||
// dcache internals
|
||||
output logic SelAdr,
|
||||
output logic ClearValid,
|
||||
output logic ClearDirty,
|
||||
output logic SetDirty,
|
||||
output logic SetValid,
|
||||
output logic SelEvict,
|
||||
output logic LRUWriteEn,
|
||||
output logic SelFlush,
|
||||
output logic FlushAdrCntEn,
|
||||
output logic FlushWayCntEn,
|
||||
output logic FlushAdrCntRst,
|
||||
output logic FlushWayCntRst,
|
||||
output logic save,
|
||||
output logic restore);
|
||||
output logic SelAdr,
|
||||
output logic ClearValid,
|
||||
output logic ClearDirty,
|
||||
output logic SetDirty,
|
||||
output logic SetValid,
|
||||
output logic SelEvict,
|
||||
output logic LRUWriteEn,
|
||||
output logic SelFlush,
|
||||
output logic FlushAdrCntEn,
|
||||
output logic FlushWayCntEn,
|
||||
output logic FlushAdrCntRst,
|
||||
output logic FlushWayCntRst,
|
||||
output logic SelBusBuffer,
|
||||
output logic SRAMEnable);
|
||||
|
||||
logic resetDelay;
|
||||
logic AMO;
|
||||
@ -87,14 +88,9 @@ module cachefsm
|
||||
typedef enum logic [3:0] {STATE_READY, // hit states
|
||||
// miss states
|
||||
STATE_MISS_FETCH_WDV,
|
||||
STATE_MISS_FETCH_DONE,
|
||||
STATE_MISS_EVICT_DIRTY_START,
|
||||
STATE_MISS_EVICT_DIRTY,
|
||||
STATE_MISS_WRITE_CACHE_LINE,
|
||||
STATE_MISS_READ_WORD,
|
||||
STATE_MISS_READ_WORD_DELAY,
|
||||
STATE_MISS_WRITE_WORD,
|
||||
// cpu stalled replay/restore state
|
||||
STATE_CPU_BUSY,
|
||||
// flush cache
|
||||
STATE_FLUSH,
|
||||
STATE_FLUSH_CHECK,
|
||||
@ -115,7 +111,7 @@ module cachefsm
|
||||
assign DoRead = CacheRW[1] & ~IgnoreRequest;
|
||||
assign DoWrite = CacheRW[0] & ~IgnoreRequest;
|
||||
|
||||
assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit;
|
||||
assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit & ~InvalidateCache;
|
||||
assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit;
|
||||
assign DoAnyHit = DoAnyUpdateHit | (DoRead & CacheHit);
|
||||
assign FlushFlag = FlushAdrFlag & FlushWayFlag;
|
||||
@ -136,26 +132,17 @@ module cachefsm
|
||||
always_comb begin
|
||||
NextState = STATE_READY;
|
||||
case (CurrState)
|
||||
STATE_READY: if(IgnoreRequest) NextState = STATE_READY;
|
||||
STATE_READY: if(IgnoreRequest | InvalidateCache) NextState = STATE_READY;
|
||||
else if(DoFlush) NextState = STATE_FLUSH;
|
||||
else if(DoAnyHit & CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // change
|
||||
else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // fetch first, then eviction is necessary. see delay in lru read/write path.
|
||||
else NextState = STATE_READY;
|
||||
STATE_MISS_FETCH_WDV: if(CacheBusAck) NextState = STATE_MISS_FETCH_DONE;
|
||||
STATE_MISS_FETCH_WDV: if(CacheBusAck & ~VictimDirty) NextState = STATE_MISS_WRITE_CACHE_LINE;
|
||||
else if(CacheBusAck & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY_START;
|
||||
else NextState = STATE_MISS_FETCH_WDV;
|
||||
STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY;
|
||||
else NextState = STATE_MISS_WRITE_CACHE_LINE;
|
||||
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD;
|
||||
STATE_MISS_READ_WORD: if(CacheRW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD;
|
||||
else NextState = STATE_MISS_READ_WORD_DELAY;
|
||||
STATE_MISS_READ_WORD_DELAY: if(CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY; // cpu_busy not needed. load misses have the property of reading from the bus buffer rather than sram.
|
||||
STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE;
|
||||
else NextState = STATE_MISS_EVICT_DIRTY;
|
||||
STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
STATE_MISS_EVICT_DIRTY_START: NextState = STATE_MISS_EVICT_DIRTY; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
|
||||
STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
|
||||
STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK;
|
||||
else if(FlushFlag) NextState = STATE_READY;
|
||||
@ -175,10 +162,9 @@ module cachefsm
|
||||
assign CacheCommitted = CurrState != STATE_READY;
|
||||
assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAnyMiss)) |
|
||||
(CurrState == STATE_MISS_FETCH_WDV) |
|
||||
(CurrState == STATE_MISS_FETCH_DONE) |
|
||||
(CurrState == STATE_MISS_EVICT_DIRTY_START) |
|
||||
(CurrState == STATE_MISS_EVICT_DIRTY) |
|
||||
(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
|
||||
(CurrState == STATE_MISS_READ_WORD) |
|
||||
(CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
|
||||
(CurrState == STATE_FLUSH) |
|
||||
(CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) |
|
||||
(CurrState == STATE_FLUSH_INCR) |
|
||||
@ -187,16 +173,15 @@ module cachefsm
|
||||
// write enables internal to cache
|
||||
assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
|
||||
assign SetDirty = (CurrState == STATE_READY & DoAnyUpdateHit) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY & AMO) |
|
||||
(CurrState == STATE_MISS_WRITE_WORD);
|
||||
(CurrState == STATE_MISS_WRITE_CACHE_LINE & (AMO | CacheRW[0]));
|
||||
assign ClearValid = '0;
|
||||
assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
|
||||
assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) |
|
||||
(CurrState == STATE_FLUSH_CLEAR_DIRTY);
|
||||
assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY) |
|
||||
(CurrState == STATE_MISS_WRITE_WORD);
|
||||
(CurrState == STATE_MISS_WRITE_CACHE_LINE);
|
||||
// Flush and eviction controls
|
||||
assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY);
|
||||
assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY_START) |
|
||||
(CurrState == STATE_MISS_EVICT_DIRTY);
|
||||
assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
|
||||
(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) |
|
||||
(CurrState == STATE_FLUSH_CLEAR_DIRTY);
|
||||
@ -209,29 +194,22 @@ module cachefsm
|
||||
assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
|
||||
// Bus interface controls
|
||||
assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss);
|
||||
assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) |
|
||||
assign CacheWriteLine = (CurrState == STATE_MISS_EVICT_DIRTY_START) |
|
||||
(CurrState == STATE_FLUSH_CHECK & VictimDirty);
|
||||
// handle cpu stall.
|
||||
assign restore = ((CurrState == STATE_CPU_BUSY)) & ~`REPLAY;
|
||||
assign save = ((CurrState == STATE_READY & DoAnyHit & CPUBusy) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | CacheRW[1]) & CPUBusy) |
|
||||
(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
|
||||
|
||||
// **** can this be simplified?
|
||||
assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.
|
||||
// use the raw requests as we don't want IgnoreRequestTrapM in the critical path
|
||||
(CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed
|
||||
(CurrState == STATE_READY & (CacheRW[1] & CacheHit) & (CPUBusy & `REPLAY)) |
|
||||
|
||||
(CurrState == STATE_READY & (DoAnyMiss)) |
|
||||
(CurrState == STATE_MISS_FETCH_WDV) |
|
||||
(CurrState == STATE_MISS_FETCH_DONE) |
|
||||
(CurrState == STATE_MISS_EVICT_DIRTY) |
|
||||
(CurrState == STATE_MISS_EVICT_DIRTY_START) |
|
||||
(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
|
||||
(CurrState == STATE_MISS_READ_WORD) |
|
||||
(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) |
|
||||
(CurrState == STATE_MISS_WRITE_WORD) |
|
||||
|
||||
(CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) |
|
||||
resetDelay;
|
||||
|
||||
assign SelBusBuffer = CurrState == STATE_MISS_WRITE_CACHE_LINE;
|
||||
assign SRAMEnable = (CurrState == STATE_READY & ~CPUBusy | CacheStall) | (CurrState != STATE_READY) | reset;
|
||||
//assign SRAMEnable = 1;
|
||||
|
||||
endmodule // cachefsm
|
||||
|
||||
42
pipelined/src/cache/cacheway.sv
vendored
42
pipelined/src/cache/cacheway.sv
vendored
@ -33,6 +33,7 @@
|
||||
module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) (
|
||||
input logic clk,
|
||||
input logic ce,
|
||||
input logic reset,
|
||||
|
||||
input logic [$clog2(NUMLINES)-1:0] RAdr,
|
||||
@ -48,16 +49,19 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
input logic VictimWay,
|
||||
input logic FlushWay,
|
||||
input logic Invalidate,
|
||||
input logic [(`XLEN-1)/8:0] ByteMask,
|
||||
// input logic [(`XLEN-1)/8:0] ByteMask,
|
||||
input logic [LINELEN/8-1:0] LineByteMask,
|
||||
|
||||
output logic [LINELEN-1:0] ReadDataLineWay,
|
||||
output logic HitWay,
|
||||
output logic VictimDirtyWay,
|
||||
output logic [TAGLEN-1:0] VictimTagWay);
|
||||
|
||||
localparam WORDSPERLINE = LINELEN/`XLEN;
|
||||
localparam integer WORDSPERLINE = LINELEN/`XLEN;
|
||||
localparam integer BYTESPERLINE = LINELEN/8;
|
||||
localparam LOGWPL = $clog2(WORDSPERLINE);
|
||||
localparam LOGXLENBYTES = $clog2(`XLEN/8);
|
||||
localparam integer BYTESPERWORD = `XLEN/8;
|
||||
|
||||
logic [NUMLINES-1:0] ValidBits;
|
||||
logic [NUMLINES-1:0] DirtyBits;
|
||||
@ -69,12 +73,15 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
logic SelTag;
|
||||
logic [$clog2(NUMLINES)-1:0] RAdrD;
|
||||
logic [2**LOGWPL-1:0] MemPAdrDecoded;
|
||||
logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn;
|
||||
logic [(`XLEN-1)/8:0] FinalByteMask;
|
||||
logic SelectedWriteWordEn;
|
||||
// logic [WORDSPERLINE-1:0] SelectedWriteWordEn;
|
||||
// logic [(`XLEN-1)/8:0] FinalByteMask;
|
||||
logic [LINELEN/8-1:0] FinalByteMask;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Write Enable demux
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
if(`LLEN>`XLEN)begin
|
||||
logic [2**LOGWPL-1:0] MemPAdrDecodedtmp;
|
||||
onehotdecoder #(LOGWPL) adrdec(
|
||||
@ -83,15 +90,16 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
end else
|
||||
onehotdecoder #(LOGWPL) adrdec(
|
||||
.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
// If writing the whole line set all write enables to 1, else only set the correct word.
|
||||
assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND
|
||||
assign FinalByteMask = SetValidWay ? '1 : ByteMask; // OR
|
||||
assign SelectedWriteWordEn = SetValidWay | SetDirtyWay;// ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND
|
||||
assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Tag Array
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk,
|
||||
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce,
|
||||
.Adr(RAdr), .ReadData(ReadTag), .ByteMask('1),
|
||||
.CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(SetValidWay));
|
||||
|
||||
@ -105,13 +113,19 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
// Data Array
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// *** instantiate one larger RAM, not one per RAM. Expand byte mask
|
||||
genvar words;
|
||||
for(words = 0; words < LINELEN/`XLEN; words++) begin: word
|
||||
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk, .Adr(RAdr),
|
||||
.ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
|
||||
.CacheWriteData(CacheWriteData[(words+1)*`XLEN-1:words*`XLEN]),
|
||||
.WriteEnable(SelectedWriteWordEn[words]), .ByteMask(FinalByteMask));
|
||||
|
||||
localparam integer SRAMLEN = 128;
|
||||
localparam integer NUMSRAM = LINELEN/SRAMLEN;
|
||||
localparam integer SRAMLENINBYTES = SRAMLEN/8;
|
||||
localparam integer LOGNUMSRAM = $clog2(NUMSRAM);
|
||||
|
||||
for(words = 0; words < NUMSRAM; words++) begin: word
|
||||
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .Adr(RAdr),
|
||||
.ReadData(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
|
||||
.CacheWriteData(CacheWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
|
||||
//.WriteEnable(1'b1), .ByteMask(SRAMLineByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
|
||||
.WriteEnable(SelectedWriteWordEn), .ByteMask(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
|
||||
end
|
||||
|
||||
// AND portion of distributed read multiplexers
|
||||
@ -127,7 +141,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
|
||||
else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1;
|
||||
else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0;
|
||||
end
|
||||
flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
|
||||
flopen #($clog2(NUMLINES)) RAdrDelayReg(clk, ce, RAdr, RAdrD);
|
||||
assign Valid = ValidBits[RAdrD];
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
7
pipelined/src/cache/sram1p1rw.sv
vendored
7
pipelined/src/cache/sram1p1rw.sv
vendored
@ -37,6 +37,7 @@
|
||||
|
||||
module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
|
||||
input logic clk,
|
||||
input logic ce,
|
||||
input logic [$clog2(DEPTH)-1:0] Adr,
|
||||
input logic [WIDTH-1:0] CacheWriteData,
|
||||
input logic WriteEnable,
|
||||
@ -46,7 +47,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
|
||||
logic [WIDTH-1:0] StoredData[DEPTH-1:0];
|
||||
logic [$clog2(DEPTH)-1:0] AdrD;
|
||||
|
||||
always_ff @(posedge clk) AdrD <= Adr;
|
||||
always_ff @(posedge clk) if(ce) AdrD <= Adr;
|
||||
|
||||
genvar index;
|
||||
|
||||
@ -66,13 +67,13 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
|
||||
end else begin
|
||||
if (WIDTH%8 != 0) // handle msbs if not a multiple of 8
|
||||
always_ff @(posedge clk)
|
||||
if (WriteEnable & ByteMask[WIDTH/8])
|
||||
if (ce & WriteEnable & ByteMask[WIDTH/8])
|
||||
StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1
|
||||
CacheWriteData[WIDTH-1:WIDTH-WIDTH%8];
|
||||
|
||||
for(index = 0; index < WIDTH/8; index++)
|
||||
always_ff @(posedge clk)
|
||||
if(WriteEnable & ByteMask[index])
|
||||
if(ce & WriteEnable & ByteMask[index])
|
||||
StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
|
||||
|
||||
assign ReadData = StoredData[AdrD];
|
||||
|
||||
12
pipelined/src/cache/subcachelineread.sv
vendored
12
pipelined/src/cache/subcachelineread.sv
vendored
@ -31,10 +31,7 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)(
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr,
|
||||
input logic save, restore,
|
||||
input logic [LINELEN-1:0] ReadDataLine,
|
||||
output logic [WORDLEN-1:0] ReadDataWord);
|
||||
|
||||
@ -43,7 +40,6 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)(
|
||||
localparam PADLEN = WORDLEN-MUXINTERVAL;
|
||||
logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
|
||||
logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
|
||||
logic [WORDLEN-1:0] ReadDataWordRaw, ReadDataWordSaved;
|
||||
|
||||
if (PADLEN > 0) begin
|
||||
logic [PADLEN-1:0] Pad;
|
||||
@ -56,11 +52,5 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)(
|
||||
assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)];
|
||||
end
|
||||
// variable input mux
|
||||
// *** maybe remove REPLAY config later after deciding which way is best
|
||||
assign ReadDataWordRaw = ReadDataLineSets[PAdr];
|
||||
if(!`REPLAY) begin
|
||||
flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved);
|
||||
mux2 #(WORDLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved,
|
||||
restore, ReadDataWord);
|
||||
end else assign ReadDataWord = ReadDataWordRaw;
|
||||
assign ReadDataWord = ReadDataLineSets[PAdr];
|
||||
endmodule
|
||||
|
||||
@ -62,36 +62,31 @@ endmodule
|
||||
// Square Root OTFC, Radix 2 //
|
||||
///////////////////////////////
|
||||
module sotfc2(
|
||||
input logic clk,
|
||||
input logic Start,
|
||||
input logic sp, sn,
|
||||
input logic Sqrt,
|
||||
input logic [`DIVLEN+3:0] C,
|
||||
output logic [`DIVLEN-2:0] Sq,
|
||||
output logic [`DIVLEN+3:0] S, SM
|
||||
input logic sp, sz,
|
||||
input logic [`DIVb-1:0] C,
|
||||
input logic [`DIVb:0] S, SM,
|
||||
output logic [`DIVb:0] SNext, SMNext
|
||||
);
|
||||
// The on-the-fly converter transfers the square root
|
||||
// bits to the quotient as they come.
|
||||
// Use this otfc for division and square root.
|
||||
logic [`DIVLEN+3:0] SNext, SMNext, SMux;
|
||||
logic [`DIVb:0] CExt;
|
||||
|
||||
flopr #(`DIVLEN+4) SMreg(clk, Start, SMNext, SM);
|
||||
mux2 #(`DIVLEN+4) Smux(SNext, {3'b000, Sqrt, {(`DIVLEN){1'b0}}}, Start, SMux);
|
||||
flop #(`DIVLEN+4) Sreg(clk, SMux, S);
|
||||
assign CExt = {1'b1, C};
|
||||
|
||||
always_comb begin
|
||||
if (sp) begin
|
||||
SNext = S | (C & ~(C << 1));
|
||||
SNext = S | (CExt & ~(CExt << 1));
|
||||
SMNext = S;
|
||||
end else if (sn) begin
|
||||
SNext = SM | (C & ~(C << 1));
|
||||
SMNext = SM;
|
||||
end else begin // If sp and sn are not true, then sz is
|
||||
end else if (sz) begin
|
||||
SNext = S;
|
||||
SMNext = SM | (C & ~(C << 1));
|
||||
SMNext = SM | (CExt & ~(CExt << 1));
|
||||
end else begin // If sp and sz are not true, then sn is
|
||||
SNext = SM | (CExt & ~(CExt << 1));
|
||||
SMNext = SM;
|
||||
end
|
||||
end
|
||||
assign Sq = S[`DIVLEN] ? S[`DIVLEN-1:1] : S[`DIVLEN-2:0];
|
||||
|
||||
endmodule
|
||||
|
||||
module otfc4 (
|
||||
|
||||
@ -66,25 +66,29 @@ endmodule
|
||||
// Adder Input Generation, Radix 2 //
|
||||
////////////////////////////////////
|
||||
module fgen2 (
|
||||
input logic sp, sn,
|
||||
input logic [`DIVLEN+3:0] C, S, SM,
|
||||
output logic [`DIVLEN+3:0] F
|
||||
input logic sp, sz,
|
||||
input logic [`DIVb-1:0] C,
|
||||
input logic [`DIVb:0] S, SM,
|
||||
output logic [`DIVb+3:0] F
|
||||
);
|
||||
logic [`DIVLEN+3:0] FP, FN, FZ;
|
||||
|
||||
logic [`DIVb+3:0] FP, FN, FZ;
|
||||
logic [`DIVb+3:0] SExt, SMExt, CExt;
|
||||
|
||||
assign SExt = {3'b0, S};
|
||||
assign SMExt = {3'b0, SM};
|
||||
assign CExt = {4'hf, C};
|
||||
|
||||
// Generate for both positive and negative bits
|
||||
assign FP = ~(S << 1) & C;
|
||||
assign FN = (SM << 1) | (C & (~C << 2));
|
||||
assign FP = ~(SExt << 1) & CExt;
|
||||
assign FN = (SMExt << 1) | (CExt & (~CExt << 2));
|
||||
assign FZ = '0;
|
||||
|
||||
// Choose which adder input will be used
|
||||
|
||||
always_comb
|
||||
if (sp) F = FP;
|
||||
else if (sn) F = FN;
|
||||
else F = FZ;
|
||||
|
||||
// assign F = sp ? FP : (sn ? FN : FZ);
|
||||
else if (sz) F = FZ;
|
||||
else F = FN;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -72,6 +72,7 @@ module srt(
|
||||
logic [`DIVN-2:0] D; // U0.N-1
|
||||
logic [`DIVb+3:0] DBar, D2, DBar2; // Q4.N-1
|
||||
logic [`DIVb:0] QMMux;
|
||||
logic [`DIVb-1:0] NextC;
|
||||
logic [`DIVb-1:0] CMux;
|
||||
logic [`DIVb:0] SMux;
|
||||
|
||||
@ -86,11 +87,22 @@ module srt(
|
||||
if (`RADIX == 2) begin : nextw
|
||||
assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
|
||||
assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
|
||||
assign NextC = {1'b1, C[`DIVCOPIES-1][`DIVb-1:1]};
|
||||
end else begin
|
||||
assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
|
||||
assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
|
||||
assign NextC = {2'b11, C[`DIVCOPIES-1][`DIVb-1:2]};
|
||||
end
|
||||
|
||||
|
||||
// mux2 #(`DIVb+4) wsmux(NextWSN, {{3{Sqrt}}, X}, DivStart, WSN); //*** modified for sqrt which doesnt work
|
||||
// flopen #(`DIVb+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]);
|
||||
// mux2 #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN);
|
||||
// flopen #(`DIVb+4) wcflop(clk, DivStart|DivBusy, WCN, WC[0]);
|
||||
// flopen #(`DIVN-1) dflop(clk, DivStart, Dpreproc, D);
|
||||
// mux2 #(`DIVb) Cmux(NextC, {Sqrt, {(`DIVb-1){1'b0}}}, DivStart, CMux);
|
||||
// flop #(`DIVb) cflop(clk, CMux, C[0]);
|
||||
|
||||
mux2 #(`DIVb+4) wsmux(NextWSN, {3'b0, X}, DivStart, WSN);
|
||||
flopen #(`DIVb+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]);
|
||||
mux2 #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN);
|
||||
@ -132,6 +144,7 @@ module srt(
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// if starting a new divison set Q to 0 and QM to -1
|
||||
mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux);
|
||||
flopenr #(`DIVb+1) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]);
|
||||
@ -196,6 +209,7 @@ module divinteration (
|
||||
// 0001 = -2
|
||||
if(`RADIX == 2) begin : qsel
|
||||
qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz);
|
||||
fgen2 fgen2(.sp(qp), .sz(qz), .C, .S, .SM, .F);
|
||||
end else begin
|
||||
qsel4 qsel4(.D, .WS, .WC, .Sqrt, .q);
|
||||
// fgen4 fgen4(.s(q), .C, .S, .SM, .F);
|
||||
@ -218,13 +232,14 @@ module divinteration (
|
||||
// WSA, WCA = WS + WC - qD
|
||||
assign AddIn = Sqrt ? F : Dsel;
|
||||
if (`RADIX == 2) begin : csa
|
||||
csa #(`DIVb+4) csa(WS, WC, AddIn, qp, WSA, WCA);
|
||||
csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~Sqrt, WSA, WCA);
|
||||
end else begin
|
||||
csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~Sqrt, WSA, WCA);
|
||||
end
|
||||
|
||||
if (`RADIX == 2) begin : otfc
|
||||
otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext);
|
||||
sotfc2 sotfc2(.sp(qp), .sz(qz), .C, .S, .SM, .SNext, .SMNext);
|
||||
end else begin
|
||||
otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
|
||||
// sotfc4 sotfc4(.s(q), .Sqrt, .C, .S, .SM, .SNext, .SMNext);
|
||||
@ -254,3 +269,7 @@ module csa #(parameter N=69) (
|
||||
assign out2 = {in1[N-2:0] & (in2[N-2:0] | in3[N-2:0]) |
|
||||
(in2[N-2:0] & in3[N-2:0]), cin};
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -236,7 +236,7 @@ module ifu (
|
||||
.Atomic('0), .FlushCache('0),
|
||||
.NextAdr(PCNextFSpill[11:0]),
|
||||
.PAdr(PCPF),
|
||||
.CacheCommitted(), .InvalidateCacheM(InvalidateICacheM));
|
||||
.CacheCommitted(), .InvalidateCache(InvalidateICacheM));
|
||||
|
||||
end else begin : passthrough
|
||||
assign {ICacheFetchLine, ICacheBusAdr, ICacheStallF, FinalInstrRawF} = '0;
|
||||
|
||||
@ -249,7 +249,7 @@ module lsu (
|
||||
.IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM(1'b0), .CacheCommitted(DCacheCommittedM),
|
||||
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
|
||||
.CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine),
|
||||
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
|
||||
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
|
||||
|
||||
end else begin : passthrough
|
||||
assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
|
||||
|
||||
@ -89,7 +89,8 @@ logic [3:0] dummy;
|
||||
if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
|
||||
else tests = {arch64c};
|
||||
"arch64m": if (`M_SUPPORTED) tests = arch64m;
|
||||
"arch64d": if (`D_SUPPORTED) tests = arch64d;
|
||||
"arch64f": if (`D_SUPPORTED) tests = arch64f;
|
||||
"arch32f": if (`F_SUPPORTED) tests = arch32f; // 32-bit FP tests r "arch64d": if (`D_SUPPORTED) tests = arch64d;
|
||||
"imperas64i": tests = imperas64i;
|
||||
"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
|
||||
"imperas64d": if (`D_SUPPORTED) tests = imperas64d;
|
||||
@ -112,9 +113,9 @@ logic [3:0] dummy;
|
||||
else tests = {arch32c};
|
||||
"arch32m": if (`M_SUPPORTED) tests = arch32m;
|
||||
"arch32f": if (`F_SUPPORTED) tests = arch32f;
|
||||
"arch32d": if (`D_SUPPORTED) tests = arch32d;
|
||||
"imperas32i": tests = imperas32i;
|
||||
"imperas32f": if (`F_SUPPORTED) tests = imperas32f;
|
||||
// "wally32d": if (`D_SUPPORTED) tests = wally32d;
|
||||
"imperas32m": if (`M_SUPPORTED) tests = imperas32m;
|
||||
"wally32a": if (`A_SUPPORTED) tests = wally32a;
|
||||
"imperas32c": if (`C_SUPPORTED) tests = imperas32c;
|
||||
@ -442,8 +443,13 @@ module DCacheFlushFSM
|
||||
localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
|
||||
localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
|
||||
localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
|
||||
localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
|
||||
localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
|
||||
|
||||
//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM;
|
||||
localparam integer numwords = sramlen/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer loglinebytelen = $clog2(linebytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
localparam integer tagstart = lognumlines + loglinebytelen;
|
||||
@ -451,16 +457,17 @@ module DCacheFlushFSM
|
||||
|
||||
|
||||
genvar index, way, cacheWord;
|
||||
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic [sramlen-1:0] cacheline;
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
for(index = 0; index < numlines; index++) begin
|
||||
for(way = 0; way < numways; way++) begin
|
||||
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
|
||||
for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
|
||||
copyShadow #(.tagstart(tagstart),
|
||||
.loglinebytelen(loglinebytelen))
|
||||
.loglinebytelen(loglinebytelen), .sramlen(sramlen))
|
||||
copyShadow(.clk,
|
||||
.start,
|
||||
.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]),
|
||||
@ -478,18 +485,25 @@ module DCacheFlushFSM
|
||||
end
|
||||
end
|
||||
|
||||
integer i, j, k;
|
||||
integer i, j, k, l;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (start) begin #1
|
||||
#1
|
||||
for(i = 0; i < numlines; i++) begin
|
||||
for(j = 0; j < numways; j++) begin
|
||||
for(k = 0; k < numwords; k++) begin
|
||||
if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin
|
||||
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
|
||||
for(l = 0; l < cachesramwords; l++) begin
|
||||
if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
|
||||
for(k = 0; k < numwords; k++) begin
|
||||
//cacheline = CacheData[j][i][0];
|
||||
// does not work with modelsim
|
||||
// # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
|
||||
// see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
|
||||
//ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k];
|
||||
ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
@ -499,15 +513,15 @@ module DCacheFlushFSM
|
||||
endmodule
|
||||
|
||||
module copyShadow
|
||||
#(parameter tagstart, loglinebytelen)
|
||||
#(parameter tagstart, loglinebytelen, sramlen)
|
||||
(input logic clk,
|
||||
input logic start,
|
||||
input logic [`PA_BITS-1:tagstart] tag,
|
||||
input logic valid, dirty,
|
||||
input logic [`XLEN-1:0] data,
|
||||
input logic [sramlen-1:0] data,
|
||||
input logic [32-1:0] index,
|
||||
input logic [32-1:0] cacheWord,
|
||||
output logic [`XLEN-1:0] CacheData,
|
||||
output logic [sramlen-1:0] CacheData,
|
||||
output logic [`PA_BITS-1:0] CacheAdr,
|
||||
output logic [`XLEN-1:0] CacheTag,
|
||||
output logic CacheValid,
|
||||
@ -520,7 +534,7 @@ module copyShadow
|
||||
CacheValid = valid;
|
||||
CacheDirty = dirty;
|
||||
CacheData = data;
|
||||
CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8));
|
||||
CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
|
||||
end
|
||||
end
|
||||
|
||||
@ -546,4 +560,4 @@ task automatic updateProgramAddrLabelArray;
|
||||
end
|
||||
$fclose(ProgramLabelMapFP);
|
||||
$fclose(ProgramAddrMapFP);
|
||||
endtask
|
||||
endtask
|
||||
|
||||
@ -1052,6 +1052,157 @@ string imperas32f[] = '{
|
||||
"rv64i_m/I/src/xori-01.S"
|
||||
};
|
||||
|
||||
string arch64f[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/F/src/fadd_b10-01.S",
|
||||
"rv64i_m/F/src/fadd_b1-01.S",
|
||||
"rv64i_m/F/src/fadd_b11-01.S",
|
||||
"rv64i_m/F/src/fadd_b12-01.S",
|
||||
"rv64i_m/F/src/fadd_b13-01.S",
|
||||
"rv64i_m/F/src/fadd_b2-01.S",
|
||||
"rv64i_m/F/src/fadd_b3-01.S",
|
||||
"rv64i_m/F/src/fadd_b4-01.S",
|
||||
"rv64i_m/F/src/fadd_b5-01.S",
|
||||
"rv64i_m/F/src/fadd_b7-01.S",
|
||||
"rv64i_m/F/src/fadd_b8-01.S",
|
||||
"rv64i_m/F/src/fclass_b1-01.S",
|
||||
"rv64i_m/F/src/fcvt.s.w_b25-01.S",
|
||||
"rv64i_m/F/src/fcvt.s.w_b26-01.S",
|
||||
"rv64i_m/F/src/fcvt.s.wu_b25-01.S",
|
||||
"rv64i_m/F/src/fcvt.s.wu_b26-01.S",
|
||||
"rv64i_m/F/src/fcvt.w.s_b1-01.S",
|
||||
"rv64i_m/F/src/fcvt.w.s_b22-01.S",
|
||||
"rv64i_m/F/src/fcvt.w.s_b23-01.S",
|
||||
"rv64i_m/F/src/fcvt.w.s_b24-01.S",
|
||||
"rv64i_m/F/src/fcvt.w.s_b27-01.S",
|
||||
"rv64i_m/F/src/fcvt.w.s_b28-01.S",
|
||||
"rv64i_m/F/src/fcvt.w.s_b29-01.S",
|
||||
"rv64i_m/F/src/fcvt.wu.s_b1-01.S",
|
||||
"rv64i_m/F/src/fcvt.wu.s_b22-01.S",
|
||||
"rv64i_m/F/src/fcvt.wu.s_b23-01.S",
|
||||
"rv64i_m/F/src/fcvt.wu.s_b24-01.S",
|
||||
"rv64i_m/F/src/fcvt.wu.s_b27-01.S",
|
||||
"rv64i_m/F/src/fcvt.wu.s_b28-01.S",
|
||||
"rv64i_m/F/src/fcvt.wu.s_b29-01.S",
|
||||
"rv64i_m/F/src/fdiv_b1-01.S",
|
||||
"rv64i_m/F/src/fdiv_b20-01.S",
|
||||
"rv64i_m/F/src/fdiv_b2-01.S",
|
||||
"rv64i_m/F/src/fdiv_b21-01.S",
|
||||
"rv64i_m/F/src/fdiv_b3-01.S",
|
||||
"rv64i_m/F/src/fdiv_b4-01.S",
|
||||
"rv64i_m/F/src/fdiv_b5-01.S",
|
||||
"rv64i_m/F/src/fdiv_b6-01.S",
|
||||
"rv64i_m/F/src/fdiv_b7-01.S",
|
||||
"rv64i_m/F/src/fdiv_b8-01.S",
|
||||
"rv64i_m/F/src/fdiv_b9-01.S",
|
||||
"rv64i_m/F/src/feq_b1-01.S",
|
||||
"rv64i_m/F/src/feq_b19-01.S",
|
||||
"rv64i_m/F/src/fle_b1-01.S",
|
||||
"rv64i_m/F/src/fle_b19-01.S",
|
||||
"rv64i_m/F/src/flt_b1-01.S",
|
||||
"rv64i_m/F/src/flt_b19-01.S",
|
||||
// "rv64i_m/F/src/flw-align-01.S",
|
||||
"rv64i_m/F/src/fmadd_b1-01.S",
|
||||
"rv64i_m/F/src/fmadd_b14-01.S",
|
||||
// "rv64i_m/F/src/fmadd_b15-01.S",
|
||||
"rv64i_m/F/src/fmadd_b16-01.S",
|
||||
"rv64i_m/F/src/fmadd_b17-01.S",
|
||||
"rv64i_m/F/src/fmadd_b18-01.S",
|
||||
"rv64i_m/F/src/fmadd_b2-01.S",
|
||||
"rv64i_m/F/src/fmadd_b3-01.S",
|
||||
"rv64i_m/F/src/fmadd_b4-01.S",
|
||||
"rv64i_m/F/src/fmadd_b5-01.S",
|
||||
"rv64i_m/F/src/fmadd_b6-01.S",
|
||||
"rv64i_m/F/src/fmadd_b7-01.S",
|
||||
"rv64i_m/F/src/fmadd_b8-01.S",
|
||||
"rv64i_m/F/src/fmax_b1-01.S",
|
||||
"rv64i_m/F/src/fmax_b19-01.S",
|
||||
"rv64i_m/F/src/fmin_b1-01.S",
|
||||
"rv64i_m/F/src/fmin_b19-01.S",
|
||||
"rv64i_m/F/src/fmsub_b1-01.S",
|
||||
"rv64i_m/F/src/fmsub_b14-01.S",
|
||||
"rv64i_m/F/src/fmsub_b15-01.S",
|
||||
"rv64i_m/F/src/fmsub_b16-01.S",
|
||||
"rv64i_m/F/src/fmsub_b17-01.S",
|
||||
"rv64i_m/F/src/fmsub_b18-01.S",
|
||||
"rv64i_m/F/src/fmsub_b2-01.S",
|
||||
"rv64i_m/F/src/fmsub_b3-01.S",
|
||||
"rv64i_m/F/src/fmsub_b4-01.S",
|
||||
"rv64i_m/F/src/fmsub_b5-01.S",
|
||||
"rv64i_m/F/src/fmsub_b6-01.S",
|
||||
"rv64i_m/F/src/fmsub_b7-01.S",
|
||||
"rv64i_m/F/src/fmsub_b8-01.S",
|
||||
"rv64i_m/F/src/fmul_b1-01.S",
|
||||
"rv64i_m/F/src/fmul_b2-01.S",
|
||||
"rv64i_m/F/src/fmul_b3-01.S",
|
||||
"rv64i_m/F/src/fmul_b4-01.S",
|
||||
"rv64i_m/F/src/fmul_b5-01.S",
|
||||
"rv64i_m/F/src/fmul_b6-01.S",
|
||||
"rv64i_m/F/src/fmul_b7-01.S",
|
||||
"rv64i_m/F/src/fmul_b8-01.S",
|
||||
"rv64i_m/F/src/fmul_b9-01.S",
|
||||
"rv64i_m/F/src/fmv.w.x_b25-01.S",
|
||||
"rv64i_m/F/src/fmv.w.x_b26-01.S",
|
||||
"rv64i_m/F/src/fmv.x.w_b1-01.S",
|
||||
"rv64i_m/F/src/fmv.x.w_b22-01.S",
|
||||
"rv64i_m/F/src/fmv.x.w_b23-01.S",
|
||||
"rv64i_m/F/src/fmv.x.w_b24-01.S",
|
||||
"rv64i_m/F/src/fmv.x.w_b27-01.S",
|
||||
"rv64i_m/F/src/fmv.x.w_b28-01.S",
|
||||
"rv64i_m/F/src/fmv.x.w_b29-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b1-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b14-01.S",
|
||||
// "rv64i_m/F/src/fnmadd_b15-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b16-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b17-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b18-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b2-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b3-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b4-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b5-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b6-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b7-01.S",
|
||||
"rv64i_m/F/src/fnmadd_b8-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b1-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b14-01.S",
|
||||
// "rv64i_m/F/src/fnmsub_b15-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b16-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b17-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b18-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b2-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b3-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b4-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b5-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b6-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b7-01.S",
|
||||
"rv64i_m/F/src/fnmsub_b8-01.S",
|
||||
"rv64i_m/F/src/fsgnj_b1-01.S",
|
||||
"rv64i_m/F/src/fsgnjn_b1-01.S",
|
||||
"rv64i_m/F/src/fsgnjx_b1-01.S",
|
||||
// "rv64i_m/F/src/fsqrt_b1-01.S",
|
||||
// "rv64i_m/F/src/fsqrt_b20-01.S",
|
||||
// "rv64i_m/F/src/fsqrt_b2-01.S",
|
||||
// "rv64i_m/F/src/fsqrt_b3-01.S",
|
||||
// "rv64i_m/F/src/fsqrt_b4-01.S",
|
||||
// "rv64i_m/F/src/fsqrt_b5-01.S",
|
||||
// "rv64i_m/F/src/fsqrt_b7-01.S",
|
||||
// "rv64i_m/F/src/fsqrt_b8-01.S",
|
||||
// "rv64i_m/F/src/fsqrt_b9-01.S",
|
||||
"rv64i_m/F/src/fsub_b10-01.S",
|
||||
"rv64i_m/F/src/fsub_b1-01.S",
|
||||
"rv64i_m/F/src/fsub_b11-01.S",
|
||||
"rv64i_m/F/src/fsub_b12-01.S",
|
||||
"rv64i_m/F/src/fsub_b13-01.S",
|
||||
"rv64i_m/F/src/fsub_b2-01.S",
|
||||
"rv64i_m/F/src/fsub_b3-01.S",
|
||||
"rv64i_m/F/src/fsub_b4-01.S",
|
||||
"rv64i_m/F/src/fsub_b5-01.S",
|
||||
"rv64i_m/F/src/fsub_b7-01.S",
|
||||
"rv64i_m/F/src/fsub_b8-01.S"
|
||||
// "rv64i_m/F/src/fsw-align-01.S"
|
||||
};
|
||||
|
||||
|
||||
string arch64d[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/D/src/fadd.d_b10-01.S",
|
||||
@ -1408,6 +1559,153 @@ string imperas32f[] = '{
|
||||
// "rv32i_m/F/src/fsw-align-01.S"
|
||||
};
|
||||
|
||||
string arch32d[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/D/src/fadd.d_b10-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b1-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b11-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b12-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b13-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b2-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b3-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b4-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b5-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b7-01.S",
|
||||
"rv32i_m/D/src/fadd.d_b8-01.S",
|
||||
"rv32i_m/D/src/fclass.d_b1-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b1-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b22-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b23-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b24-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b27-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b28-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.s_b29-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.w_b25-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.w_b26-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.wu_b25-01.S",
|
||||
"rv32i_m/D/src/fcvt.d.wu_b26-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b1-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b22-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b23-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b24-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b27-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b28-01.S",
|
||||
"rv32i_m/D/src/fcvt.s.d_b29-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b1-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b22-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b23-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b24-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b27-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b28-01.S",
|
||||
"rv32i_m/D/src/fcvt.w.d_b29-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b1-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b22-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b23-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b24-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b27-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b28-01.S",
|
||||
"rv32i_m/D/src/fcvt.wu.d_b29-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b1-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b20-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b2-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b21-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b3-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b4-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b5-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b6-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b7-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b8-01.S",
|
||||
"rv32i_m/D/src/fdiv.d_b9-01.S",
|
||||
"rv32i_m/D/src/feq.d_b1-01.S",
|
||||
"rv32i_m/D/src/feq.d_b19-01.S",
|
||||
"rv32i_m/D/src/fle.d_b1-01.S",
|
||||
"rv32i_m/D/src/fle.d_b19-01.S",
|
||||
"rv32i_m/D/src/flt.d_b1-01.S",
|
||||
"rv32i_m/D/src/flt.d_b19-01.S",
|
||||
// "rv32i_m/D/src/fld-align-01.S", //missing right now from top of tree, should be returned when it comes back
|
||||
// "rv32i_m/D/src/fsd-align-01.S", //https://github.com/riscv-non-isa/riscv-arch-test/issues/266
|
||||
"rv32i_m/D/src/fmadd.d_b14-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b16-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b17-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b18-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b2-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b3-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b4-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b5-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b6-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b7-01.S",
|
||||
"rv32i_m/D/src/fmadd.d_b8-01.S",
|
||||
"rv32i_m/D/src/fmax.d_b1-01.S",
|
||||
"rv32i_m/D/src/fmax.d_b19-01.S",
|
||||
"rv32i_m/D/src/fmin.d_b1-01.S",
|
||||
"rv32i_m/D/src/fmin.d_b19-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b14-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b16-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b17-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b18-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b2-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b3-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b4-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b5-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b6-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b7-01.S",
|
||||
"rv32i_m/D/src/fmsub.d_b8-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b1-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b2-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b3-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b4-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b5-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b6-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b7-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b8-01.S",
|
||||
"rv32i_m/D/src/fmul.d_b9-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b14-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b16-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b17-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b18-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b2-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b3-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b4-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b5-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b6-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b7-01.S",
|
||||
"rv32i_m/D/src/fnmadd.d_b8-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b14-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b16-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b17-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b18-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b2-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b3-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b4-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b5-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b6-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b7-01.S",
|
||||
"rv32i_m/D/src/fnmsub.d_b8-01.S",
|
||||
"rv32i_m/D/src/fsgnj.d_b1-01.S",
|
||||
"rv32i_m/D/src/fsgnjn.d_b1-01.S",
|
||||
"rv32i_m/D/src/fsgnjx.d_b1-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b1-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b20-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b2-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b3-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b4-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b5-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b7-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b8-01.S",
|
||||
// "rv32i_m/D/src/fsqrt.d_b9-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b10-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b1-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b11-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b12-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b13-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b2-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b3-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b4-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b5-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b7-01.S",
|
||||
"rv32i_m/D/src/fssub.d_b8-01.S"
|
||||
};
|
||||
|
||||
|
||||
string arch32c[] = '{
|
||||
`RISCVARCHTEST,
|
||||
@ -1611,4 +1909,4 @@ string imperas32f[] = '{
|
||||
string wally32d[] = '{
|
||||
`WALLYTEST,
|
||||
"rv32i_m/D/src/WALLY-fld.S"
|
||||
};
|
||||
};
|
||||
|
||||
@ -51,7 +51,7 @@ lappend search_path ./mapped
|
||||
|
||||
# Set up User Information
|
||||
set company "Oklahoma State University"
|
||||
set user "James E. Stine"
|
||||
set user "Prof. James E. Stine"
|
||||
|
||||
# Alias
|
||||
alias ra report_area
|
||||
|
||||
@ -27,7 +27,7 @@ set maxopt $::env(MAXOPT)
|
||||
set drive $::env(DRIVE)
|
||||
|
||||
eval file copy -force ${cfg} {$outputDir/hdl/}
|
||||
eval file copy -force ${cfg} $outputDir
|
||||
#eval file copy -force ${cfg} $outputDir
|
||||
eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/}
|
||||
eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
|
||||
eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {$outputDir/hdl/}
|
||||
|
||||
@ -6,16 +6,19 @@ arch_workdir = $(work)/riscv-arch-test
|
||||
wally_workdir = $(work)/wally-riscv-arch-test
|
||||
|
||||
current_dir = $(shell pwd)
|
||||
XLEN ?= 64
|
||||
#XLEN ?= 64
|
||||
|
||||
all: root build_rv32e build_wally build_arch
|
||||
all: root fsd_fld_tempfix arch32 wally32 wally32e arch64 wally64
|
||||
#all: root fsd_fld_tempfix arch64
|
||||
|
||||
root:
|
||||
mkdir -p $(work_dir)
|
||||
mkdir -p $(work)
|
||||
mkdir -p $(arch_workdir)
|
||||
mkdir -p $(wally_workdir)
|
||||
sed 's,{0},$(current_dir),g;s,{1},$(XLEN)$(if $(findstring 64,$(XLEN)),gc,imc),g' config.ini > config$(XLEN).ini
|
||||
sed 's,{0},$(current_dir),g;s,{1},32imc,g' config.ini > config32.ini
|
||||
sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini
|
||||
sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
|
||||
|
||||
fsd_fld_tempfix:
|
||||
# this is a temporary fix, there's a typo on the rv64i_m/D/src/d_fsd-align-01.S and rv64i_m/D/src/d_fld-align-01.S tests
|
||||
@ -23,27 +26,30 @@ fsd_fld_tempfix:
|
||||
find ../../addins/riscv-arch-test/riscv-test-suite -type f -name "*d_fld-align*.S" | xargs -I{} sed -i 's,regex(\.\*32\.\*),regex(\.\*64\.\*),g' {}
|
||||
find ../../addins/riscv-arch-test/riscv-test-suite -type f -name "*d_fsd-align*.S" | xargs -I{} sed -i 's,regex(\.\*32\.\*),regex(\.\*64\.\*),g' {}
|
||||
|
||||
build_arch: fsd_fld_tempfix
|
||||
riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
|
||||
# rm -rf $(arch_workdir)/rv$(XLEN)i_m
|
||||
rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
|
||||
rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
|
||||
arch32:
|
||||
riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
|
||||
rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed"
|
||||
|
||||
build_wally:
|
||||
riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
|
||||
# riscof --verbose debug run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run 2>&1 | tee log.txt
|
||||
# rm -rf $(wally_workdir)/rv$(XLEN)i_m
|
||||
# mv -f $(work_dir)/rv$(XLEN)i_m $(wally_workdir)/
|
||||
rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
|
||||
rsync -a $(work_dir)/rv64i_m/ $(wally_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
|
||||
arch64:
|
||||
riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
|
||||
rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed"
|
||||
# Also copy F and D tests to RV64
|
||||
rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed"
|
||||
|
||||
build_rv32e:
|
||||
sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
|
||||
wally32:
|
||||
riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
|
||||
rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"
|
||||
|
||||
wally64:
|
||||
riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
|
||||
rsync -a $(work_dir)/rv64i_m/ $(wally_workdir)/rv64i_m/ || echo "error suppressed"
|
||||
|
||||
wally32e:
|
||||
riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
|
||||
# riscof --verbose debug run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run 2>&1 | tee log.txt
|
||||
rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"
|
||||
rsync -a $(work_dir)/rv32e_unratified/ $(wally_workdir)/rv32e_unratified/ || echo "error suppressed"
|
||||
|
||||
|
||||
memfile:
|
||||
find $(work) -type f -name "*.elf" | grep "rv64i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 64 --input "$$f" --output "$$f.memfile"; done
|
||||
find $(work) -type f -name "*.elf" | grep "rv32i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done
|
||||
@ -55,4 +61,4 @@ clean:
|
||||
rm -f config32e.ini
|
||||
rm -rf $(work_dir)
|
||||
rm -rf $(wally_workdir)
|
||||
rm -rf $(arch_workdir)
|
||||
rm -rf $(arch_workdir)
|
||||
|
||||
@ -127,4 +127,6 @@ class sail_cSim(pluginTemplate):
|
||||
execute+=coverage_cmd
|
||||
|
||||
make.add_target(execute)
|
||||
make.execute_all(self.work_dir)
|
||||
# make.execute_all(self.work_dir)
|
||||
# DH 7/26/22 increase timeout so sim will finish on slow machines
|
||||
make.execute_all(self.work_dir, timeout = 600)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user