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@ -52,16 +52,128 @@ RVTEST_CODE_BEGIN
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// address for stack
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la sp, top_of_stack
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// trap handler setup
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la x1, machine_trap_handler
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csrrw x4, mtvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
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.endm
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// Code to trigger traps goes here so we have consistent mtvals for instruction adresses
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// Even if more tests are added.
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.macro CAUSE_TRAP_TRIGGERS
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j end_trap_triggers
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// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
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// This effectively includes everything that isn't to do with page faults (virtual memory)
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cause_instr_addr_misaligned:
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// cause a misaligned address trap
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auipc x28, 0 // get current PC, which is aligned
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addi x28, x28, 0x3 // add 1 to pc to create misaligned address
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jr x28 // cause instruction address midaligned trap
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ret
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cause_instr_access:
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la x28, 0x0 // address zero is an address with no memory
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sw x1, -4(sp) // push the return adress ontot the stack
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addi sp, sp, -4
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jalr x28 // cause instruction access trap
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lw x1, 0(sp) // pop return adress back from the stack
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addi sp, sp, 4
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ret
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cause_illegal_instr:
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.word 0x00000000 // a 32 bit zros is an illegal instruction
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ret
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cause_breakpnt: // ****
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ebreak
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ret
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cause_load_addr_misaligned:
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auipc x28, 0 // get current PC, which is aligned
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addi x28, x28, 1
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lw x29, 0(x28) // load from a misaligned address
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ret
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cause_load_acc:
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la x28, 0 // 0 is an address with no memory
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lw x29, 0(x28) // load from unimplemented address
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ret
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cause_store_addr_misaligned:
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auipc x28, 0 // get current PC, which is aligned
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addi x28, x28, 1
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sw x29, 0(x28) // store to a misaligned address
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ret
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cause_store_acc:
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la x28, 0 // 0 is an address with no memory
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sw x29, 0(x28) // store to unimplemented address
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ret
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cause_ecall:
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// *** ASSUMES you have already gone to the mode you need to call this from.
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ecall
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ret
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cause_time_interrupt:
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// The following code works for both RV32 and RV64.
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// RV64 alone would be easier using double-word adds and stores
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li x28, 0x30 // Desired offset from the present time
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la x29, 0x02004000 // MTIMECMP register in CLINT
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la x30, 0x0200BFF8 // MTIME register in CLINT
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lw x7, 0(x30) // low word of MTIME
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lw x31, 4(x30) // high word of MTIME
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add x28, x7, x28 // add desired offset to the current time
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bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound)
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addi x31, x31, 1 // if wrap, increment most significant word
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sw x31,4(x29) // store into most significant word of MTIMECMP
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nowrap:
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sw x28, 0(x29) // store into least significant word of MTIMECMP
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loop: j loop // wait until interrupt occurs
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ret
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cause_soft_interrupt:
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la x28, 0x02000000 // MSIP register in CLINT
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li x29, 1 // 1 in the lsb
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sw x29, 0(x28) // Write MSIP bit
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ret
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cause_ext_interrupt:
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li x28, 0x10060000 // load base GPIO memory location
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li x29, 0x1
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sw x29, 8(x28) // enable the first pin as an output
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sw x29, 28(x28) // set first pin to high interrupt enable
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sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
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ret
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end_trap_triggers:
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.endm
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.macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0
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// MODE decides which mode this trap handler will be taken in (M or S mode)
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// Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1)
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// vs Using the non-vector approach the rest of the trap handler takes (0)
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// DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1)
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// vs not saving that info to the signature (0)
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// Set up the exception Handler, keeping the original handler in x4.
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la x1, trap_handler_\MODE\()
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ori x1, x1, \VECTORED // set mode field of tvec to VECTORED, which will force vectored interrupts if it's 1.
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.if (\MODE\() == m)
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csrrw x4, \MODE\()tvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
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.else
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csrw \MODE\()tvec, x1 // we only neet save the machine trap handler and this if statement ensures it isn't overwritten
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.endif
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li a0, 0
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li a1, 0
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li a2, 0 // reset trap handler inputs to zero
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// go to beginning of S file where we can decide between using the test data loop
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// or using the macro inline code insertion
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j s_file_begin
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la x29, 0x02004000 // MTIMECMP register in CLINT
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li x30, 0xFFFFFFFF
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sw x30, 0(x29) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
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j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
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// ---------------------------------------------------------------------------------------------
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// General traps Handler
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@ -96,38 +208,77 @@ RVTEST_CODE_BEGIN
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// --------------------------------------------------------------------------------------------
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machine_trap_handler:
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.align 2
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trap_handler_\MODE\():
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j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
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// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
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// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
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// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
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j soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
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j segfault_\MODE\() // 2: reserved
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j soft_interrupt_\MODE\() // 3: breakpoint
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j segfault_\MODE\() // 4: reserved
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j time_interrupt_\MODE\() // 5: load access fault
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j segfault_\MODE\() // 6: reserved
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j time_interrupt_\MODE\() // 7: store access fault
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j segfault_\MODE\() // 8: reserved
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j ext_interrupt_\MODE\() // 9: ecall from S-mode
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j segfault_\MODE\() // 10: reserved
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j ext_interrupt_\MODE\() // 11: ecall from M-mode
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// 12 through >=16 are reserved or designated for platform use
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trap_unvectored_\MODE\():
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// The processor is always in machine mode when a trap takes us here
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// save registers on stack before using
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sw x1, -4(sp)
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sw x5, -8(sp)
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// Record trap
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csrr x1, mcause // record the mcause
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csrr x1, \MODE\()cause // record the mcause
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sw x1, 0(x16)
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addi x6, x6, 4
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addi x16, x16, 4 // update pointers for logging results
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.if (\DEBUG\() == 1) // record extra information (MTVAL, some status bits) about traps
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csrr x1, \MODE\()tval
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sw x1, 0(x16)
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addi x6, x6, 4
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addi x16, x16, 4
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csrr x1, \MODE\()status
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.if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
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li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
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.else
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li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
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.endif
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and x5, x5, x1
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sw x5, 0(x16) // store masked out status bits to the output
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addi x6, x6, 4
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addi x16, x16, 4
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.endif
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// Respond to trap based on cause
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// All interrupts should return after being logged
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csrr x1, \MODE\()cause
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li x5, 0x8000000000000000 // if msb is set, it is an interrupt
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and x5, x5, x1
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bnez x5, trapreturn // return from interrupt
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bnez x5, trapreturn_\MODE\() // return from interrupt
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// Other trap handling is specified in the vector Table
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slli x1, x1, 2 // multiply cause by 4 to get offset in vector Table
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la x5, trap_handler_vector_table
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la x5, exception_vector_table_\MODE\()
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add x5, x5, x1 // compute address of vector in Table
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lw x5, 0(x5) // fectch address of handler from vector Table
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jr x5 // and jump to the handler
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segfault:
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segfault_\MODE\():
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lw x5, -8(sp) // restore registers from stack before faulting
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lw x1, -4(sp)
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j terminate_test // halt program.
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trapreturn:
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trapreturn_\MODE\():
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// look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
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csrr x1, mepc // get the mepc
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csrr x1, \MODE\()epc // get the mepc
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addi x1, x1, 4 // *** should be 2 for compressed instructions, see note.
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@ -151,13 +302,13 @@ trapreturn:
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// csrr x1, mepc // get the mepc again
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// addi x1, x1, 4 // add 4 to find the next instruction
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trapreturn_specified:
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trapreturn_specified_\MODE\():
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// reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
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// so that when we return to a new virtual address, they're all in the right spot as well.
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beqz a1, trapreturn_finished // either update values, of go to default return address.
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beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address.
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la x5, trap_return_pagetype_table
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la x5, trap_return_pagetype_table_\MODE\()
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slli a2, a2, 2
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add x5, x5, a2
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lw a2, 0(x5) // a2 = number of offset bits in current page type
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@ -189,54 +340,93 @@ trapreturn_specified:
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li a1, 0
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li a2, 0 // reset trapreturn inputs to the trap handler
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trapreturn_finished:
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csrw mepc, x1 // update the mepc with address of next instruction
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trapreturn_finished_\MODE\():
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csrw \MODE\()epc, x1 // update the mepc with address of next instruction
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lw x5, -8(sp) // restore registers from stack before returning
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lw x1, -4(sp)
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mret // return from trap
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\MODE\()ret // return from trap
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ecallhandler:
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ecallhandler_\MODE\():
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// Check input parameter a0. encoding above.
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// *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs.
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li x5, 2 // case 2: change to machine mode
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beq a0, x5, ecallhandler_changetomachinemode
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beq a0, x5, ecallhandler_changetomachinemode_\MODE\()
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li x5, 3 // case 3: change to supervisor mode
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beq a0, x5, ecallhandler_changetosupervisormode
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beq a0, x5, ecallhandler_changetosupervisormode_\MODE\()
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li x5, 4 // case 4: change to user mode
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beq a0, x5, ecallhandler_changetousermode
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beq a0, x5, ecallhandler_changetousermode_\MODE\()
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// unsupported ecalls should segfault
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j segfault
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j segfault_\MODE\()
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ecallhandler_changetomachinemode:
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ecallhandler_changetomachinemode_\MODE\():
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// Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret
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li x1, 0b1100000000000
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csrs mstatus, x1
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j trapreturn
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csrs \MODE\()status, x1
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j trapreturn_\MODE\()
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ecallhandler_changetosupervisormode:
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ecallhandler_changetosupervisormode_\MODE\():
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// Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret
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li x1, 0b1100000000000
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csrc mstatus, x1
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csrc \MODE\()status, x1
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li x1, 0b0100000000000
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csrs mstatus, x1
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j trapreturn
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csrs \MODE\()status, x1
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j trapreturn_\MODE\()
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ecallhandler_changetousermode:
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ecallhandler_changetousermode_\MODE\():
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// Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
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li x1, 0b1100000000000
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csrc mstatus, x1
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j trapreturn
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csrc \MODE\()status, x1
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j trapreturn_\MODE\()
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instrfault:
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instrpagefault_\MODE\():
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lw x1, -4(sp) // load return address int x1 (the address AFTER the jal into faulting page)
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j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
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j trapreturn_finished_\MODE\() // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
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illegalinstr:
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j trapreturn // return to the code after recording the mcause
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instrfault_\MODE\():
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lw x1, -4(sp) // load return address int x1 (the address AFTER the jal to the faulting address)
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j trapreturn_finished_\MODE\() // return to the code after recording the mcause
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accessfault:
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illegalinstr_\MODE\():
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j trapreturn_\MODE\() // return to the code after recording the mcause
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accessfault_\MODE\():
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// *** What do I have to do here?
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j trapreturn
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j trapreturn_\MODE\()
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addr_misaligned_\MODE\():
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j trapreturn_\MODE\()
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breakpt_\MODE\():
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j trapreturn_\MODE\()
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soft_interrupt_\MODE\():
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li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table.
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sw x5, 0(x16)
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addi x6, x6, 4
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addi x16, x16, 4
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la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
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sw x0, 0(x28)
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j trap_unvectored_\MODE\()
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time_interrupt_\MODE\():
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li x5, 0x7EC
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sw x5, 0(x16)
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addi x6, x6, 4
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addi x16, x16, 4
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la x29, 0x02004000 // MTIMECMP register in CLINT
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li x30, 0xFFFFFFFF
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sw x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
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j trap_unvectored_\MODE\()
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ext_interrupt_\MODE\():
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li x5, 0x7EC
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sw x5, 0(x16)
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addi x6, x6, 4
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addi x16, x16, 4
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li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
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sw x0, 8(x28) // disable the first pin as an output
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sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
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j trap_unvectored_\MODE\()
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// Table of trap behavior
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// lists what to do on each exception (not interrupts)
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@ -244,29 +434,30 @@ accessfault:
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// Expected exceptions should increment the EPC to the next instruction and return
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.align 2 // aligns this data table to an 4 byte boundary
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trap_handler_vector_table:
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.4byte segfault // 0: instruction address misaligned
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.4byte instrfault // 1: instruction access fault
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.4byte illegalinstr // 2: illegal instruction
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.4byte segfault // 3: breakpoint
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.4byte segfault // 4: load address misaligned
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.4byte accessfault // 5: load access fault
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.4byte segfault // 6: store address misaligned
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.4byte accessfault // 7: store access fault
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.4byte ecallhandler // 8: ecall from U-mode
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.4byte ecallhandler // 9: ecall from S-mode
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.4byte segfault // 10: reserved
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.4byte ecallhandler // 11: ecall from M-mode
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.4byte instrfault // 12: instruction page fault
|
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.4byte trapreturn // 13: load page fault
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.4byte segfault // 14: reserved
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.4byte trapreturn // 15: store page fault
|
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exception_vector_table_\MODE\():
|
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|
.4byte addr_misaligned_\MODE\() // 0: instruction address misaligned
|
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|
.4byte instrfault_\MODE\() // 1: instruction access fault
|
|
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|
.4byte illegalinstr_\MODE\() // 2: illegal instruction
|
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|
.4byte breakpt_\MODE\() // 3: breakpoint
|
|
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|
|
.4byte addr_misaligned_\MODE\() // 4: load address misaligned
|
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|
.4byte accessfault_\MODE\() // 5: load access fault
|
|
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|
.4byte addr_misaligned_\MODE\() // 6: store address misaligned
|
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|
.4byte accessfault_\MODE\() // 7: store access fault
|
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|
.4byte ecallhandler_\MODE\() // 8: ecall from U-mode
|
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|
.4byte ecallhandler_\MODE\() // 9: ecall from S-mode
|
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|
.4byte segfault_\MODE\() // 10: reserved
|
|
|
|
|
.4byte ecallhandler_\MODE\() // 11: ecall from M-mode
|
|
|
|
|
.4byte instrpagefault_\MODE\() // 12: instruction page fault
|
|
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|
|
.4byte trapreturn_\MODE\() // 13: load page fault
|
|
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|
.4byte segfault_\MODE\() // 14: reserved
|
|
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|
.4byte trapreturn_\MODE\() // 15: store page fault
|
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|
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|
.align 2
|
|
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|
|
trap_return_pagetype_table:
|
|
|
|
|
trap_return_pagetype_table_\MODE\():
|
|
|
|
|
.4byte 0xC // 0: kilopage has 12 offset bits
|
|
|
|
|
.4byte 0x16 // 1: megapage has 22 offset bits
|
|
|
|
|
|
|
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|
|
trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler and continue with the test
|
|
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|
|
.endm
|
|
|
|
|
|
|
|
|
|
// Test Summary table!
|
|
|
|
|
@ -367,7 +558,7 @@ trap_return_pagetype_table:
|
|
|
|
|
// they generally do not fault or cause issues as long as these modes are enabled
|
|
|
|
|
// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
|
|
|
|
|
|
|
|
|
|
.macro GOTO_M_MODE RETURN_VPN RETURN_PAGETYPE
|
|
|
|
|
.macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
|
|
|
|
|
li a0, 2 // determine trap handler behavior (go to machine mode)
|
|
|
|
|
li a1, \RETURN_VPN // return VPN
|
|
|
|
|
li a2, \RETURN_PAGETYPE // return page types
|
|
|
|
|
@ -375,7 +566,7 @@ trap_return_pagetype_table:
|
|
|
|
|
// now in S mode
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro GOTO_S_MODE RETURN_VPN RETURN_PAGETYPE
|
|
|
|
|
.macro GOTO_S_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
|
|
|
|
|
li a0, 3 // determine trap handler behavior (go to supervisor mode)
|
|
|
|
|
li a1, \RETURN_VPN // return VPN
|
|
|
|
|
li a2, \RETURN_PAGETYPE // return page types
|
|
|
|
|
@ -383,7 +574,7 @@ trap_return_pagetype_table:
|
|
|
|
|
// now in S mode
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro GOTO_U_MODE RETURN_VPN RETURN_PAGETYPE
|
|
|
|
|
.macro GOTO_U_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
|
|
|
|
|
li a0, 4 // determine trap handler behavior (go to user mode)
|
|
|
|
|
li a1, \RETURN_VPN // return VPN
|
|
|
|
|
li a2, \RETURN_PAGETYPE // return page types
|
|
|
|
|
|
Kip Macsai-Goren