Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

ported fixes to 32 bit tests

Browse Source
This commit is contained in:
Kip Macsai-Goren 2023-03-22 23:16:57 -07:00
parent ff59fefcc9
commit 758da62a9f
2 changed files with 3 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
View File

@ -29,10 +29,6 @@
00000008 # scause from U mode ecall
00000000 # stval of ecall (*** defined to be zero for now)
00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
0007ec01 # value to indicate successful vectoring on s soft interrupt
80000001 # scause value from s soft interrupt
00000000 # stval for ssoft interrupt (0x0)
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
0007ec03 # value to indicate successful vectoring on m soft interrupt
80000003 # scause value from m soft interrupt
00000000 # stval for msoft interrupt (0x0)

6
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
View File

@ -57,12 +57,12 @@ GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
// some interrupts excluded becaus writing MIP is illegal from S mode
jal cause_s_soft_interrupt
// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9)
//jal cause_s_soft_interrupt
jal cause_m_soft_interrupt
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt