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Refactored setup QUESTA and SNPS paths, and removed troublesome bit manipulation test cases
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setup.sh
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setup.sh
@ -2,7 +2,7 @@
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# setup.sh
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# David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021
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# Set up tools for riscv-wally
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# Set up tools for rvw
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echo "Executing Wally setup.sh"
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@ -15,14 +15,15 @@ echo \$WALLY set to ${WALLY}
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# Must edit these based on your local environment. Ask your sysadmin.
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export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
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export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
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export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Questa
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export PATH=/cad/synopsys/SYN/bin:$PATH # Change this for your path to Design Compiler
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export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa
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export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler
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# Path to RISC-V Tools
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export RISCV=/opt/riscv # change this if you installed the tools in a different location
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# Tools
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# Questa and Synopsys
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export PATH=$QUESTAPATH:$SNPSPATH:$PATH
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# GCC
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export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
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export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools
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hart_ids: [0]
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hart0:
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ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
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ISA: RV32IMAFDCZicsr_Zifencei
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# ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
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physical_addr_sz: 32
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User_Spec_Version: '2.3'
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supported_xlen: [32]
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hart_ids: [0]
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hart0:
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ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
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ISA: RV64IMAFDCSUZicsr_Zifencei
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# ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
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physical_addr_sz: 56
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User_Spec_Version: '2.3'
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supported_xlen: [64]
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