Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Removed test cases irrelevant to this implementation, added explanatory comments.

Browse Source
This commit is contained in:
Kip Macsai-Goren 2022-04-22 23:06:52 +00:00
parent 3e62a8f974
commit b277d3cf19
4 changed files with 10 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
View File

@ -52,9 +52,9 @@ GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
// some interrupts excluded becaus writing MIP is illegal from S mode
jal cause_s_soft_interrupt
jal cause_m_soft_interrupt
//jal cause_s_time_interrupt // *** S time interrupts cannot come from S mode as of 4/19/22.
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
@ -84,13 +84,10 @@ jal cause_store_acc
GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
jal cause_s_soft_interrupt // *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests
jal cause_s_soft_interrupt
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
END_TESTS

11
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
View File

@ -50,9 +50,8 @@ jal cause_store_addr_misaligned
jal cause_store_acc
jal cause_ecall
//jal cause_s_soft_interrupt // *** writing SIP from u mode is illegal
// some interrupts excluded becaus writing SIP/MIP is illegal from U mode
jal cause_m_soft_interrupt
//jal cause_s_time_interrupt // *** S time interrupts cannot come from U mode as of 4/19/22.
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
@ -81,15 +80,9 @@ jal cause_store_addr_misaligned
jal cause_store_acc
jal cause_ecall
//jal cause_s_soft_interrupt // *** S Soft interrupts cannot be caused from u mode since writing SIP is illegal
// *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
END_TESTS

10
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
View File

@ -52,9 +52,9 @@ GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
// some interrupts excluded becaus writing MIP is illegal from S mode
jal cause_s_soft_interrupt
jal cause_m_soft_interrupt
//jal cause_s_time_interrupt // *** S time interrupts cannot come from S mode as of 4/19/22.
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
@ -84,14 +84,10 @@ jal cause_store_acc
GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
jal cause_s_soft_interrupt // *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests
jal cause_s_soft_interrupt
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
END_TESTS

11
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S
View File

@ -50,9 +50,8 @@ jal cause_store_addr_misaligned
jal cause_store_acc
jal cause_ecall
//jal cause_s_soft_interrupt // *** writing SIP from u mode is illegal
// some interrupts excluded becaus writing SIP/MIP is illegal from U mode
jal cause_m_soft_interrupt
//jal cause_s_time_interrupt // *** S time interrupts cannot come from U mode as of 4/19/22.
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
@ -81,15 +80,9 @@ jal cause_store_addr_misaligned
jal cause_store_acc
jal cause_ecall
//jal cause_s_soft_interrupt // *** S Soft interrupts cannot be caused from u mode since writing SIP is illegal
// *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
END_TESTS