Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 02:05:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

split status.fp tests into fp enabled/disabled

Browse Source
This commit is contained in:
Kip Macsai-Goren 2022-04-25 19:16:15 +00:00
parent da29193f9b
commit 7e6fefb2d9
5 changed files with 1072 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
View File

@ -70,7 +70,8 @@ target_tests_nosim = \
WALLY-trap-u-01 \
WALLY-status-tw-01 \
WALLY-WFI-01 \
WALLY-status-fp-01 \
WALLY-status-fp-enabled-01 \
WALLY-status-fp-disabled-01 \
# Have all 0's in references!
#WALLY-MEPC \
#WALLY-SEPC \

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-01.reference_output → tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-disabled-01.reference_output
View File

@ -1,11 +1,3 @@
00002000 # read SD = 0, FS = 01
00000000
00006000 # read SD = 1, FS = 11
80000000
00002000 # read written SD = 1, FS = 01
00000000
00006000 # read SD = 1, FS = 11
80000000
00000000 # read SD = 0, FS = 00 after diabling floating point
00000000
00000000 # read SD = 0, FS = 00 after attempting to write to diabled bits

1020
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output Normal file
View File

File diff suppressed because it is too large Load Diff

49
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-disabled-01.S Normal file
View File

@ -0,0 +1,49 @@
///////////////////////////////////////////
//
// WALLY-status-floating-point
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-24
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
TRAP_HANDLER m
// Misa.F is already 0 in this config, making floating point diabled
li x28, 0x8000000000006000 // mask bits for SD and FS bits of status csr
csrr x29, mstatus
and x29, x29, x28
sd x29, 0(x6) // read disabled FS, SD bits, which should both be 0
addi x6, x6, 8
addi x16, x16, 8
csrs mstatus, x28 // attempt to write 11 and 1 to fs and sd in mstatus (this should not work)
csrr x29, mstatus
and x29, x29, x28
sd x29, 0(x6) // read disabled FS, SD bits, which should both be 0
addi x6, x6, 8
addi x16, x16, 8
END_TESTS
TEST_STACK_AND_DATA

36
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-01.S → tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S
View File

@ -27,15 +27,10 @@ INIT_TESTS
TRAP_HANDLER m
// Misa.F is already 1 in this config, aking floating point enabled
# li x29, 0x28
# csrs misa, x29 // disable floating point and double floating point
// Misa.F is already 1 in this config, making floating point enabled
li x28, 0x8000000000006000 // mask bits for SD and FS bits of status csr
li x29, 0x2000
csrs mstatus, x29 // turn on FS for spike???
csrr x29, mstatus
and x29, x29, x28
sd x29, 0(x6) // read initial FS, SD bits, which should be 01 and 0 respectively
@ -69,35 +64,6 @@ sd x29, 0(x6) // read dirty FS, SD bits, which should be 11 and 1 respectively
addi x6, x6, 8
addi x16, x16, 8
// fp_supported_success:
// sw x0, 0(x6) // write a zero to signature to indicate successful test
// addi x6, x6, 8
// addi x16, x16, 8
// j fp_unsupported
// fp_supported_failure:
// li x29, 0x1
// sw x29, 0(x6)
// addi x6, x6, 8
// addi x16, x16, 8
// j fp_unsupported
li x29, 0x28
csrc misa, x29 // disable floating point and double floating point
csrr x29, mstatus
and x29, x29, x28
sd x29, 0(x6) // read disabled FS, SD bits, which should both be 0
addi x6, x6, 8
addi x16, x16, 8
csrs mstatus, x28 // attempt to write 11 and 1 to fs and sd in mstatus (this should not work)
csrr x29, mstatus
and x29, x29, x28
sd x29, 0(x6) // read disabled FS, SD bits, which should both be 0
addi x6, x6, 8
addi x16, x16, 8
END_TESTS
TEST_STACK_AND_DATA