Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-24 05:24:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

removed changes to counteren from stimecmp tests

Browse Source
This commit is contained in:
Kip Macsai-Goren 2023-03-04 15:46:57 -08:00
parent 75f6e9eb34
commit ab6b953a4b
2 changed files with 0 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
View File

@ -136,11 +136,8 @@ time_loop_m:
ret
cause_s_time_interrupt:
li t3, 0x2
csrs mcounteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
li t3, 0x30 // Desired offset from the present time
mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles
// la t4, 0x02004000 // MTIMECMP register in CLINT
la t5, 0x0200BFF8 // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it
lw t2, 0(t5) // low word of MTIME
lw t6, 4(t5) // high word of MTIME
@ -367,9 +364,6 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w
.endif
li t3, 0x2
csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
// Respond to trap based on cause
// All interrupts should return after being logged
csrr ra, \MODE\()cause
@ -440,9 +434,6 @@ trapreturn_specified_\MODE\():
li a2, 0 // reset trapreturn inputs to the trap handler
trapreturn_finished_\MODE\():
li t3, 0x2
csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
csrw \MODE\()epc, ra // update the mepc with address of next instruction
lw t2, -12(sp) // restore registers from stack before returning
lw t0, -8(sp)

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
View File

@ -138,8 +138,6 @@ time_loop_m:
ret
cause_s_time_interrupt:
li t3, 0x2
csrs mcounteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
li t3, 0x30 // Desired offset from the present time
mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles
// la t4, 0x02004000 // MTIMECMP register in CLINT
@ -357,9 +355,6 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w
.endif
li t3, 0x2
csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
// Respond to trap based on cause
// All interrupts should return after being logged
csrr ra, \MODE\()cause
@ -430,9 +425,6 @@ trapreturn_specified_\MODE\():
li a2, 0 // reset trapreturn inputs to the trap handler
trapreturn_finished_\MODE\():
li t3, 0x2
csrc \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
csrw \MODE\()epc, ra // update the epc with address of next instruction
ld t2, -24(sp) // restore registers from stack before returning
ld t0, -16(sp)