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https://github.com/openhwgroup/cvw
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Added correct causing and handling of S time interrupts to test suite.
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Kip Macsai-Goren
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da74ed0369
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ac5c53a870
@ -125,20 +125,34 @@ cause_m_time_interrupt:
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lw t2, 0(t5) // low word of MTIME
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lw t6, 4(t5) // high word of MTIME
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add t3, t2, t3 // add desired offset to the current time
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bgtu t3, t2, nowrap // check new time exceeds current time (no wraparound)
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bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound)
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addi t6, t6, 1 // if wrap, increment most significant word
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sw t6,4(t4) // store into most significant word of MTIMECMP
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nowrap:
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nowrap_m:
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sw t3, 0(t4) // store into least significant word of MTIMECMP
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time_loop:
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time_loop_m:
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addi a3, a3, -1
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bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
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bnez a3, time_loop_m // go through this loop for [a3 value] iterations before returning without performing interrupt
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ret
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cause_s_time_interrupt:
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li t3, 0x20
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csrs mip, t3 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
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nop // added extra nops in so the csrs can get through the pipeline before returning.
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li t3, 0x2
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csrs mcounteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
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li t3, 0x30 // Desired offset from the present time
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mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles
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// la t4, 0x02004000 // MTIMECMP register in CLINT
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la t5, 0x0200BFF8 // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it
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lw t2, 0(t5) // low word of MTIME
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lw t6, 4(t5) // high word of MTIME
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add t3, t2, t3 // add desired offset to the current time
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bgtu t3, t2, nowrap_s // check new time exceeds current time (no wraparound)
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addi t6, t6, 1 // if wrap, increment most significant word
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nowrap_s:
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csrw 0x14D, t3 // store into STIMECMP
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csrw 0x15D, t6 // store into STIMECMPH
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time_loop_s:
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addi a3, a3, -1
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bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt
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ret
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cause_m_soft_interrupt:
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@ -353,6 +367,9 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w
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.endif
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li t3, 0x2
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csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
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// Respond to trap based on cause
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// All interrupts should return after being logged
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csrr ra, \MODE\()cause
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@ -423,6 +440,9 @@ trapreturn_specified_\MODE\():
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li a2, 0 // reset trapreturn inputs to the trap handler
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trapreturn_finished_\MODE\():
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li t3, 0x2
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csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
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csrw \MODE\()epc, ra // update the mepc with address of next instruction
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lw t2, -12(sp) // restore registers from stack before returning
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lw t0, -8(sp)
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@ -545,8 +565,12 @@ soft_interrupt_\MODE\():
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time_interrupt_\MODE\():
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la t0, 0x02004000 // MTIMECMP register in CLINT
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li t2, 0xFFFFFFFF
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sw t2, 0(t0) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
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sw t2, 0(t0) // reset interrupt by setting mtimecmp to max
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//sw t2, 4(t0) // reset interrupt by setting mtimecmpH to max
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csrw 0x14D, t2 // reset stime interrupts by doing the same to stimecmp and stimecmpH.
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csrw 0x15D, t2
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li t0, 0x20
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csrc \MODE\()ip, t0
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lw ra, -4(sp) // load return address from stack into ra (the address to return to after the loop is complete)
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@ -127,22 +127,32 @@ cause_m_time_interrupt:
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lw t2, 0(t5) // low word of MTIME
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lw t6, 4(t5) // high word of MTIME
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add t3, t2, t3 // add desired offset to the current time
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bgtu t3, t2, nowrap // check new time exceeds current time (no wraparound)
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bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound)
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addi t6, t6, 1 // if wrap, increment most significant word
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sw t6,4(t4) // store into most significant word of MTIMECMP
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nowrap:
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nowrap_m:
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sw t3, 0(t4) // store into least significant word of MTIMECMP
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time_loop:
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time_loop_m:
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addi a3, a3, -1
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bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
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bnez a3, time_loop_m // go through this loop for [a3 value] iterations before returning without performing interrupt
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ret
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cause_s_time_interrupt:
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li t3, 0x20
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csrs mip, t3 // set supervisor time interrupt pending.
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nop // added extra nops in so the csrs can get through the pipeline before returning.
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li t3, 0x2
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csrs mcounteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
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li t3, 0x30 // Desired offset from the present time
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mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles
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// la t4, 0x02004000 // MTIMECMP register in CLINT
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la t5, 0x0200BFF8 // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it
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lw t2, 0(t5) // low word of MTIME
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lw t6, 4(t5) // high word of MTIME
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add t3, t2, t3 // add desired offset to the current time
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csrw 0x14D, t3 // store into most significant word of STIMECMP
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time_loop_s:
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addi a3, a3, -1
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bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt
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ret
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cause_m_soft_interrupt:
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la t3, 0x02000000 // MSIP register in CLINT
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li t4, 1 // 1 in the lsb
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@ -347,6 +357,9 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w
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.endif
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li t3, 0x2
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csrs \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
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// Respond to trap based on cause
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// All interrupts should return after being logged
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csrr ra, \MODE\()cause
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@ -417,6 +430,9 @@ trapreturn_specified_\MODE\():
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li a2, 0 // reset trapreturn inputs to the trap handler
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trapreturn_finished_\MODE\():
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li t3, 0x2
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csrc \MODE\()counteren, t3 // set mcounteren.TM to 1 to attempt to allow us to write to stimecmp
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csrw \MODE\()epc, ra // update the epc with address of next instruction
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ld t2, -24(sp) // restore registers from stack before returning
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ld t0, -16(sp)
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@ -539,7 +555,8 @@ soft_interrupt_\MODE\():
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time_interrupt_\MODE\():
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la t0, 0x02004000 // MTIMECMP register in CLINT
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li t2, 0xFFFFFFFF
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sd t2, 0(t0) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
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sd t2, 0(t0) // reset interrupt by setting mtimecmp to max
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csrw 0x14D, t2 // reset stime interrupts by doing the same.
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li t0, 0x20
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csrc \MODE\()ip, t0
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