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Vectored interrupts now require 64 byte alignment.

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Eliminates adder.
This commit is contained in:
Ross Thompson 2022-12-21 12:05:49 -06:00
parent 2b1e9f8bed
commit c41d58bd29
3 changed files with 25 additions and 24 deletions
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3
pipelined/src/privileged/csr.sv
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@ -143,7 +143,8 @@ module csr #(parameter
logic VectoredM;
logic [`XLEN-1:0] TVecPlusCauseM;
assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01);
assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00};
//assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00};
assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00};
mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM);
end else
assign TrapVectorM = TVecAlignedM;

22
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
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@ -299,23 +299,23 @@ end_trap_triggers:
// --------------------------------------------------------------------------------------------
.align 2
.align 6
trap_handler_\MODE\():
j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
j segfault_\MODE\() // 2: reserved
j m_soft_vector_\MODE\() // 3: breakpoint
j segfault_\MODE\() // 4: reserved
j s_time_vector_\MODE\() // 5: load access fault
j segfault_\MODE\() // 6: reserved
j m_time_vector_\MODE\() // 7: store access fault
j segfault_\MODE\() // 8: reserved
j s_ext_vector_\MODE\() // 9: ecall from S-mode
j segfault_\MODE\() // 10: reserved
j m_ext_vector_\MODE\() // 11: ecall from M-mode
j segfault_\MODE\()
j m_soft_vector_\MODE\()
j segfault_\MODE\()
j s_time_vector_\MODE\()
j segfault_\MODE\()
j m_time_vector_\MODE\()
j segfault_\MODE\()
j s_ext_vector_\MODE\()
j segfault_\MODE\()
j m_ext_vector_\MODE\()
// 12 through >=16 are reserved or designated for platform use
trap_unvectored_\MODE\():

24
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
View File

@ -293,23 +293,23 @@ end_trap_triggers:
//
// --------------------------------------------------------------------------------------------
.align 3
.align 6
trap_handler_\MODE\():
j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
j segfault_\MODE\() // 2: reserved
j m_soft_vector_\MODE\() // 3: breakpoint
j segfault_\MODE\() // 4: reserved
j s_time_vector_\MODE\() // 5: load access fault
j segfault_\MODE\() // 6: reserved
j m_time_vector_\MODE\() // 7: store access fault
j segfault_\MODE\() // 8: reserved
j s_ext_vector_\MODE\() // 9: ecall from S-mode
j segfault_\MODE\() // 10: reserved
j m_ext_vector_\MODE\() // 11: ecall from M-mode
j s_soft_vector_\MODE\()
j segfault_\MODE\()
j m_soft_vector_\MODE\()
j segfault_\MODE\()
j s_time_vector_\MODE\()
j segfault_\MODE\()
j m_time_vector_\MODE\()
j segfault_\MODE\()
j s_ext_vector_\MODE\()
j segfault_\MODE\()
j m_ext_vector_\MODE\()
// 12 through >=16 are reserved or designated for platform use
trap_unvectored_\MODE\():