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https://github.com/openhwgroup/cvw
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updated trap handler alignemnts to 64 bytes in priv tests
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@ -299,8 +299,7 @@ end_trap_triggers:
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// --------------------------------------------------------------------------------------------
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//.align 6
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.align 2
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.align 6
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trap_handler_\MODE\():
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j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
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// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
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@ -35,8 +35,8 @@ RVTEST_CODE_BEGIN
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# ---------------------------------------------------------------------------------------------
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j main_code
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# Thanks to MTVEC[1:0], trap handler addresses need to be aligned to a 4-byte boundary
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.align 2
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# 64 byte alignment for vectored traps to align with xtev
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.align 6
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###################
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###################
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trap_handler: #####
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@ -293,8 +293,7 @@ end_trap_triggers:
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//
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// --------------------------------------------------------------------------------------------
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//.align 6
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.align 3
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.align 6
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trap_handler_\MODE\():
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j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
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// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
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@ -35,8 +35,8 @@ RVTEST_CODE_BEGIN
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# ---------------------------------------------------------------------------------------------
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j main_code
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# Thanks to MTVEC[1:0], trap handler addresses need to be aligned to a 4-byte boundary
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.align 2
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# 64 byte alignment for vectored traps to align with xtev
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.align 6
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###################
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###################
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trap_handler: #####
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