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https://github.com/openhwgroup/cvw
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GPIO tests
This commit is contained in:
David Harris
parent
d86a65daf0
commit
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@ -5,7 +5,19 @@ A5A5A5A5 # test output pins
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00000000 # test input enables
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5A5A0000
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A55A0000 # test XOR
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# A55A0000 # test interrupt pins
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# 5AA5FFFF
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# 00000000
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# 00000000
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A55A0000 # Test interrupt pending bits: high_ip
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5AA5FFFF # low_ip
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00000000 # rise_ip
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00000000 # fall_ip
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A4AA0000 # input_val
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A5FA0000 # high_ip
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5BF50000 # low_ip
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00A00000 # rise_ip
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01500000 # fall_ip
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00000000 # MEIP
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00000000 # Test interrupts can be enabled without being triggered: MIP = 0
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00000000 # MIP = 0
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00000000 # MIP = 0
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00000000 # MIP = 0
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00000800 # Test interrupts can be enabled and triggered: MEIP set
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00000000 # MEIP = 0
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@ -827,6 +827,28 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
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addi a6, a6, 4
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.endm
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// Place this macro in peripheral tests to setup all the PLIC registers to generate external interrupts
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.macro SETUP_PLIC
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# Setup PLIC with a series of register writes
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.equ PLIC_INTPRI_GPIO, 0x0C00000C # GPIO is interrupt 3
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.equ PLIC_INTPRI_UART, 0x0C000028 # UART is interrupt 10
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.equ PLIC_INTPENDING0, 0x0C001000 # intPending0 register
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.equ PLIC_INTEN00, 0x0C002000 # interrupt enables for context 0 (machine mode) sources 31:1
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.equ PLIC_INTEN10, 0x0C002080 # interrupt enables for context 1 (supervisor mode) sources 31:1
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.equ PLIC_THRESH0, 0x0C200000 # Priority threshold for context 0 (machine mode)
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.equ PLIC_CLAIM0, 0x0C200004 # Claim/Complete register for context 0
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.equ PLIC_THRESH1, 0x0C201000 # Priority threshold for context 1 (supervisor mode)
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.equ PLIC_CLAIM1, 0x0C201004 # Claim/Complete register for context 1
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.4byte PLIC_THRESH0, 0, write32_test # Set PLIC machine mode interrupt threshold to 0 to accept all interrupts
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.4byte PLIC_THRESH1, 7, write32_test # Set PLIC supervisor mode interrupt threshold to 7 to accept no interrupts
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.4byte PLIC_INTPRI_GPIO, 7, write32_test # Set GPIO to high priority
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.4byte PLIC_INTPRI_UART, 7, write32_test # Set UART to high priority
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.4byte PLIC_INTEN00, 0xFFFFFFFF, write32_test # Enable all interrupt sources for machine mode
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.4byte PLIC_INTEN10, 0x00000000, write32_test # Disable all interrupt sources for supervisor mode
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.endm
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.macro END_TESTS
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// invokes one final ecall to return to machine mode then terminates this program, so the output is
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// 0x8: termination called from U mode
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@ -937,6 +959,20 @@ read08_test:
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addi a6, a6, 4
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j test_loop // go to next test case
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readmip_test: // read the MIP into the signature
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csrr t2, mip
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sw t2, 0(t1)
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addi t1, t1, 4
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addi a6, a6, 4
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j test_loop // go to next test case
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readsip_test: // read the MIP into the signature
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csrr t2, sip
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sw t2, 0(t1)
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addi t1, t1, 4
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addi a6, a6, 4
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j test_loop // go to next test case
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goto_s_mode:
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// return to address in t3,
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li a0, 3 // Trap handler behavior (go to supervisor mode)
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@ -72,6 +72,7 @@ test_cases:
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.4byte input_val, 0x00000000, read32_test # input_val reset to zero
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.4byte input_en, 0x00000000, read32_test # input_en reset to zero
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# *** add more
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# =========== Test output and input pins ===========
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@ -86,36 +87,49 @@ test_cases:
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.4byte input_en, 0x00000000, write32_test # disable all input pins
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.4byte input_val, 0x00000000, read32_test # read 0 since input pins are disabled
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.4byte input_en, 0xFFFF0000, write32_test # enable a few input pins
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.4byte input_val, 0x5A5A0000, read32_test # read part of pattern set above.
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.4byte input_val, 0x5A5A0000, read32_test # read part of pattern set above.
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# =========== Test XOR functionality ===========
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.4byte out_xor, 0xFF00FF00, write32_test # invert certain pin values
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.4byte input_val, 0xA55A0000, read32_test # read inverted pins and verify input enable is working
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.4byte input_val, 0xA55A0000, read32_test # read inverted pins and verify input enable is working
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# =========== End of functioning tests ===========
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# # =========== Test Interrupt Pending bits ===========
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# =========== Test Interrupt Pending bits ===========
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# .4byte low_ip, 0xFFFFFFFF, write32_test # clear pending low interrupts
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# .4byte high_ip, 0xFFFFFFFF, write32_test # clear pending high interrupts
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# .4byte rise_ip, 0xFFFFFFFF, write32_test # clear pending rise interrupts
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# .4byte fall_ip, 0xFFFFFFFF, write32_test # clear pending fall interrupts
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# .4byte high_ip, 0xA55A0000, read32_test # check pending high interrupts
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# .4byte low_ip, 0x5AA5FFFF, read32_test # check pending low interrupts
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# .4byte rise_ip, 0x00000000, read32_test # check pending rise interrupts
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# .4byte fall_ip, 0x00000000, read32_test # check pending fall interrupts
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# .4byte output_val, 0x5BAA000F, write32_test # change output pattern to check rise/fall interrupts
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# .4byte input_val, 0xA4AA0000, read32_test # check new output matches expected output
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# .4byte high_ip, 0xA5FA00000, read32_test # high interrupt pending *** (is this correct?)
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# .4byte low_ip, 0x5BF50000, read32_test # low interrupt pending should be opposite high for enabled pins
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# .4byte rise_ip, 0x00A00000, read32_test # check for changed bits (rising)
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# .4byte fall_ip, 0x01500000, read32_test # check for changed bits (falling)
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SETUP_PLIC
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# # =========== Test Interrupt Enable without interrupts ===========
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.4byte low_ip, 0xFFFFFFFF, write32_test # clear pending low interrupts
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.4byte high_ip, 0xFFFFFFFF, write32_test # clear pending high interrupts
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.4byte rise_ip, 0xFFFFFFFF, write32_test # clear pending rise interrupts
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.4byte fall_ip, 0xFFFFFFFF, write32_test # clear pending fall interrupts
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.4byte high_ip, 0xA55A0000, read32_test # check pending high interrupts
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.4byte low_ip, 0x5AA5FFFF, read32_test # check pending low interrupts
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.4byte rise_ip, 0x00000000, read32_test # check pending rise interrupts
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.4byte fall_ip, 0x00000000, read32_test # check pending fall interrupts
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.4byte output_val, 0x5BAA000F, write32_test # change output pattern to check rise/fall interrupts
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.4byte input_val, 0xA4AA0000, read32_test # check new output matches expected output
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.4byte high_ip, 0xA5FA00000, read32_test # high interrupt pending *** (is this correct?)
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.4byte low_ip, 0x5BF50000, read32_test # low interrupt pending should be opposite high for enabled pins
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.4byte rise_ip, 0x00A00000, read32_test # check for changed bits (rising)
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.4byte fall_ip, 0x01500000, read32_test # check for changed bits (falling)
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.4byte 0x0, 0x00000000, readmip_test # Check no external interrupt has been generated
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# .4byte high_ie, 0x00010000, write32_test # enable high interrupt on bit 16, no pending interrupt
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# .4byte high_ip, 0xA5FA0000, read32_test # read to show no interrupt has happened
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# .4byte low_ie, 0x00020000, write32_test # enable low interrupt on bit 17, no pending interrupt
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# .4byte low_ip, 5BF50000, read32_test # read to show no interrupt has happened
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# =========== Test interrupts can be enabled without being triggered ===========
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.4byte high_ie, 0x00010000, write32_test # enable high interrupt on bit 16, no pending interrupt
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.4byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending
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.4byte low_ie, 0x00020000, write32_test # enable low interrupt on bit 17, no pending interrupt
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.4byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending
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.4byte rise_ie, 0x00010000, write32_test # enable rise interrupt on bit 16, no pending interrupt
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.4byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending
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.4byte fall_ie, 0x00010000, write32_test # enable fall interrupt on bit 16, no pending interrupt
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.4byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending
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# =========== Test interrupts can be enabled and triggered
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.4byte high_ie, 0x00020000, write32_test # enable high interrupt on bit 17, which is pending
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.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised
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.4byte low_ie, 0x00000000, write32_test # disable high interrupt on bit 17, which is pending
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.4byte 0x0, 0x00000000, readmip_test # MEIP should be released
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.4byte 0x0, 0x0, terminate_test # terminate tests
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