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645 Commits

Author SHA1 Message Date
Ross Thompson
2093e7cce3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 15:20:37 -05:00
Ross Thompson
7afbd8d877 The clock gater was not implemented correctly. Now it is level sensitive to a low clock. 2021-06-01 15:05:22 -05:00
James E. Stine
2c140679e3 Minor cosmetic update to fpu.sv 2021-06-01 15:45:32 -04:00
James E. Stine
bccdd2c137 Updates to muldiv.sv for 32-bit div/rem 2021-06-01 15:31:07 -04:00
Ross Thompson
8e330367ac added clock gater to floating point divider to speed up simulation time. 2021-06-01 13:46:21 -05:00
Ross Thompson
605ceb7ddb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 12:42:21 -05:00
Ross Thompson
f5aa5d7c67 Forgot to include the new gshare predictor file. 2021-06-01 12:42:03 -05:00
Kip Macsai-Goren
8f7e69715d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-01 13:20:39 -04:00
Ross Thompson
8f9680556f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346 Now have global history working correctly. 2021-06-01 10:57:43 -05:00
James E. Stine
927aec34a2 Modify muldiv.sv to handle W instructions for 64-bits 2021-05-31 23:27:42 -04:00
Ross Thompson
1db8d0e59c may have fixed the global branch history predictor. 
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
 2021-05-31 16:11:12 -05:00
Kip Macsai-Goren
42af5f9818 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-31 11:01:15 -04:00
James E. Stine
a71b97e878 Cosmetic changes on integer divider 2021-05-31 09:16:30 -04:00
James E. Stine
2f365a9e07 Add enhancements to integer divider including: 
- better comments
  - optimize FSM to end earlier
  - passes for 32-bit or 64-bit depending on parameter to intdiv

Left div.bak in just in case have to revert back to original for now.
 2021-05-31 09:12:21 -04:00
James E. Stine
889b935630 Modify elements of generics for LZD and shifter wrote for integer 
divider.
 2021-05-31 08:36:19 -04:00
bbracker
a45b61ede9 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
Kip Macsai-Goren
529226ac8d made priority encoder parameterizable 2021-05-28 18:09:28 -04:00
Ross Thompson
40bdcda32d It's a bit sloppy, but the global history predictor is working correctly now. 
There were two major bugs with the predictor.
First the update mechanism was completely wrong.  The PHT is updated with the GHR that was used to lookup the prediction.  PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted.  This is important so that back to back branches' GHRs are not the same.  The must be different to avoid aliasing.  Speculation of the GHR update allows them to be different.  On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed.  Updates to follow.
 2021-05-27 23:06:28 -05:00
Katherine Parry
0646e08609 classify unit created and passes imperas tests 2021-05-27 18:53:55 -04:00
Katherine Parry
65eca433b6 All compare instructions pass imperas tests 2021-05-27 15:23:28 -04:00
Katherine Parry
bd05de0dbb FADD and FSUB imperas tests pass 2021-05-26 12:33:33 -04:00
James E. Stine
e3b3321f91 delete old file for FPregfile 2021-05-26 09:13:09 -05:00
James E. Stine
cc2a7ced7f Add regression test for fpadd 2021-05-26 09:12:37 -05:00
Katherine Parry
3869a73a9c renamed top level FPU wires 2021-05-25 20:04:34 -04:00
Ross Thompson
735e511073 fixed bug with icache miss spill fsm branch. 2021-05-25 14:26:22 -05:00
James E. Stine
e32e812f6a Update FPregfile to use more compact code and better structure for ease in reading 2021-05-25 13:21:59 -05:00
Ross Thompson
aa9a81b760 Merge remote-tracking branch 'refs/remotes/origin/main' into main 2021-05-24 23:25:36 -05:00
Ross Thompson
13034c7406 Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF. 2021-05-24 23:24:54 -05:00
James E. Stine
bbc1dfb309 Minor cosmetic elements on div.sv 2021-05-24 19:30:28 -05:00
James E. Stine
1704fdc877 Mod for DIV/REM instruction and update to div.sv unit 2021-05-24 19:29:13 -05:00
Ross Thompson
3c5e87d6c2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-24 14:28:41 -05:00
Katherine Parry
03aea055fa FMV.X.D imperas test passes 2021-05-24 14:44:30 -04:00
Ross Thompson
dd26b754eb Fixed minor bug in instruction class decoding. 2021-05-24 13:41:14 -05:00
Ross Thompson
b06fda88ff Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link). 2021-05-24 12:37:16 -05:00
James E. Stine
194c32defa Update header for FPadd 2021-05-24 08:28:16 -05:00
Katherine Parry
55f22979ca FSD and FLD imperas tests pass 2021-05-23 18:33:14 -04:00
Katherine Parry
71e4a10efb FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
bbracker
8554f2f3cd plic implementation optimizations 2021-05-19 18:10:48 +00:00
Katherine Parry
409438bc95 floating point infinite loop removed from imperas tests 2021-05-18 10:42:51 -04:00
James E. Stine
49cc330bd9 Forgot initialization config for div - apologies 2021-05-17 17:12:27 -05:00
James E. Stine
96eca3287f Add 32/64-bit shifter for update to shifter block 2021-05-17 17:02:13 -05:00
James E. Stine
97cbdae674 Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
Thomas Fleming
fda439b51e Fix comment 2021-05-14 08:06:07 -04:00
Thomas Fleming
1fc607b399 Remove busy-mmu and fix missing signal 2021-05-14 07:14:20 -04:00
Thomas Fleming
980c00fa64 Clean up MMU code 2021-05-14 07:12:32 -04:00
Thomas Fleming
1e0a5ef807 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 15:22:21 -04:00
bbracker
535046e494 small synthesis fixes 2021-05-04 15:21:01 -04:00
Thomas Fleming
37bba95500 Fix compiler warning in PMP checker 2021-05-04 15:18:08 -04:00
Ross Thompson
2aa4db470b Fixed synthesis bug with icache valid bit. 2021-05-04 13:03:08 -05:00
Ross Thompson
87d3869a6e Fixed icache pcmux control for handling miss spill miss. 2021-05-04 11:05:01 -05:00
Thomas Fleming
dac07e34cf Fix bug in PMP checker 
Now we only enforce PMP regions if at least one is non-null
 2021-05-04 03:14:07 -04:00
Thomas Fleming
d7fa0903bc Disable PMP checker to fix test loops 
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
 2021-05-04 01:56:05 -04:00
Thomas Fleming
d53afc8510 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Domenico Ottolia
a7e89f43c1 Fix bug with IllegalInstrFaultM not getting correct value 2021-05-03 22:48:03 -04:00
Thomas Fleming
f78f2b3b5d Adjust attributes in PMA checker 2021-05-03 21:58:32 -04:00
David Harris
96e90402c5 Rolled back fflush on uart. Use -syncio in Modelsim command line instead. 2021-05-03 20:04:44 -04:00
David Harris
062120f944 Flush uart print statements on \n 2021-05-03 19:51:51 -04:00
David Harris
743011194b Flush uart print statements on \n 2021-05-03 19:41:37 -04:00
David Harris
8758b6efa1 Flush uart print statements on \n 2021-05-03 19:37:45 -04:00
David Harris
2f5649832a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:29:01 -04:00
David Harris
1f2da4c457 Flush uart print statements on \n 2021-05-03 19:25:28 -04:00
Ross Thompson
6a01ea9f2d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 16:57:36 -05:00
Ross Thompson
ed4f2ecb24 fixed subtle typo in icache fsm. Was messing up hit spill hit. 
I believe the mibench qsort benchmark runs after this icache fix.
 2021-05-03 16:55:36 -05:00
Domenico Ottolia
ab68933466 Fix bug that caused stvec to get the wrong value 2021-05-03 17:54:57 -04:00
Thomas Fleming
3f7061d557 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 17:38:13 -04:00
Thomas Fleming
86a93d77b4 Implement PMP checker and revise PMA checker 2021-05-03 17:37:42 -04:00
Thomas Fleming
00c3b5a033 Remove remnants of InstrReadC 2021-05-03 17:36:25 -04:00
Ross Thompson
0a44d4dd4e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 14:53:54 -05:00
Ross Thompson
e09ac73eaf Removed combinational loops between icache and PMA checker. 2021-05-03 14:51:25 -05:00
Ross Thompson
7185905f7b Reduced icache to 1 port memory. 2021-05-03 14:47:49 -05:00
Katherine Parry
3f05e31954 fpu warnings fixed/commented 2021-05-03 19:17:09 +00:00
Thomas Fleming
94d734cca9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-05-03 14:02:19 -04:00
Ross Thompson
12b978fec2 Eliminated extra register and fixed ports to icache. 
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
 2021-05-03 12:04:54 -05:00
bbracker
8ec0d18444 merge conflict resolved -- Ross and I made the same fix 2021-05-03 10:10:42 -04:00
Ross Thompson
b57c187208 Fixed typo in ifu for bypassing branch predictor. 
Fixed missing signal name in local history predictor.
 2021-05-03 08:56:45 -05:00
David Harris
c9806fb472 Fixed lint error in div 2021-05-03 09:26:12 -04:00
bbracker
fb0910d9c0 ifu lint fixes 2021-05-03 09:25:22 -04:00
bbracker
acd99be7f8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 09:23:52 -04:00
Katherine Parry
9252d08b41 fpu imperas tests run 2021-05-01 02:18:01 +00:00
bbracker
0d62440f60 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-30 06:26:35 -04:00
bbracker
9c08ce5359 rv32 plic test and lint fixes 2021-04-30 06:26:31 -04:00
Domenico Ottolia
830787e3e1 Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts 2021-04-29 20:42:14 -04:00
Thomas Fleming
10c7260980 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-29 16:30:00 -04:00
ushakya22
de23edcfb9 fix to pcm bug 2021-04-29 15:21:08 -04:00
Jarred Allen
000f48cd75 Fix compile error in branch predictor 2021-04-29 14:36:56 -04:00
Shreya Sanghai
b554dc8e72 fixed bug in gshare, global and local history BP 2021-04-29 06:14:32 -04:00
Thomas Fleming
e091f430e0 Clean up PMA checker and begin PMP checker 2021-04-29 02:20:39 -04:00
Ross Thompson
14a69c1d06 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Ross Thompson
a7e4d39ea1 Fixed issue with not saving the first cache block read on a miss spill. 2021-04-26 12:57:34 -05:00
Ross Thompson
44d28dbd1c Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
bbracker
f921886451 merge cleanup; mem init is broken 2021-04-26 08:00:17 -04:00
bbracker
7947858481 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
8d77012995 progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
46a1616079 thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
5687ab1c96 do script refactor 2021-04-24 09:32:09 -04:00
Thomas Fleming
6f23858609 Fix HSIZE and HBURST signal widths in PMA checker 2021-04-23 20:11:43 -04:00
Ross Thompson
d7fea1ba3c almost working icache. 2021-04-23 16:47:23 -05:00
Ross Thompson
c9bdaceddb Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Ross Thompson
04eb302925 Yes. The hack to not repeat the d memory operation fixed this issue. 2021-04-22 15:22:56 -05:00
Thomas Fleming
5bff582608 Write PCM to TVAL registers 2021-04-22 16:17:57 -04:00
Thomas Fleming
07770a46d8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 15:37:19 -04:00
Thomas Fleming
74fb1dccad Prepare to squash bad ahb accesses 2021-04-22 15:36:45 -04:00
Thomas Fleming
c055ab272d Clean up lint errors in fpu and muldiv 
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
 2021-04-22 15:36:03 -04:00
Domenico Ottolia
787ae978d7 Fix misa synthesis bug (for real now) 2021-04-22 15:35:20 -04:00
Thomas Fleming
e7822ce20c Implement first pass at the PMA checker 2021-04-22 15:34:02 -04:00
Thomas Fleming
805ac5dbd7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 13:20:12 -04:00
bbracker
c796547156 greatly improved PLIC register interface 2021-04-22 11:22:01 -04:00
Ross Thompson
7c8d2e9b78 Partially working icache. 
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory.  This keeps StallF high and
the icache FSM is never allowed to complete.
 2021-04-22 10:20:36 -05:00
Thomas Fleming
d22f0f9d63 Refactor tlb_ram to use flop primitives 2021-04-22 01:52:43 -04:00
Thomas Fleming
4d4ca24640 Extend stall on leaf page lookups 2021-04-22 01:51:38 -04:00
Domenico Ottolia
939e36a151 Fix misa bug 2021-04-22 00:59:07 -04:00
Thomas Fleming
88bd151d55 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-04-21 20:01:08 -04:00
Thomas Fleming
70c801331a Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Ross Thompson
50e893eec9 Fixed for the instruction spills. 2021-04-21 16:47:05 -05:00
Teo Ene
008b308b79 Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
Ross Thompson
269ea7997c major progress. 
It's running the icache is imperas tests now.
Compressed does not work yet.
 2021-04-21 08:39:54 -05:00
Domenico Ottolia
d5f86fadac Add tests for sepc register 2021-04-20 23:50:53 -04:00
Ross Thompson
a861a37b72 Why was the linter messed up? 
There are a number of combo loops which need fixing outside the icache.  They may be fixed in main.
We get to instruction address 50 now!
 2021-04-20 22:06:12 -05:00
Ross Thompson
daa1ab9261 Progress on icache. Fixed some issues aligning the PC with instruction. Still broken. 2021-04-20 21:19:53 -05:00
Ross Thompson
649589ee2c Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Domenico Ottolia
e02ff60b07 Fix synthesis warnings for privileged unit (replace 'initial' settings) 2021-04-20 17:57:56 -04:00
Jarred Allen
59b340dac9 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Katherine Parry
204e5cb018 fixed synth bugs in fpu 2021-04-19 00:39:16 +00:00
Noah Boorstin
d0a137ce0c neat verilog thing 2021-04-18 17:48:51 -04:00
Jarred Allen
3868a82932 dcache lints 2021-04-15 21:13:56 -04:00
bbracker
11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
a149f2f3d8 Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
Teo Ene
a9c6d357d8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 15:29:09 -05:00
Teo Ene
7a40c27b59 Quick fix to ahblite missing default statement done in class :) 2021-04-15 15:29:04 -05:00
Thomas Fleming
e8770e3eac Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/mmu/priority_encoder.sv
 2021-04-15 16:20:43 -04:00
Thomas Fleming
e838f0bb3d Change priority encoder to avoid extra assignment 2021-04-15 16:17:35 -04:00
Thomas Fleming
2c4682c4be Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Teo Ene
cefc8ea22b Temporary change to mmu/priority_encoder.sv 
Necessary to get synth working
Original HDL is still there, just commented out
 2021-04-15 13:37:12 -05:00
Katherine Parry
0bdd3efdd5 integraded the FMA into the FPU 2021-04-15 18:28:00 +00:00
Jarred Allen
7b4b1a31ef Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Ross Thompson
534e3eaac8 Merge branch 'bpfixes' into main 2021-04-15 09:06:21 -05:00
Shreya Sanghai
75caa65df1 Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
ShreyaSanghai
80fbd66113 added localHistoryPredictor 2021-04-15 08:58:22 -05:00
Shreya Sanghai
3696bf4f2c fixed bugs in global history to read latest GHRE 
Cherry pick Shreya's commits into main branch.
 2021-04-15 08:55:22 -05:00
bbracker
76f50d7a69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 09:06:03 -04:00
bbracker
da22308e60 csri lint improvement 2021-04-15 09:05:53 -04:00
Jarred Allen
4d58f673b2 Add a comment to explain a detail 2021-04-14 23:14:59 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
c32fe09056 More icache bugfixes 2021-04-14 19:03:33 -04:00
Jarred Allen
757b64e487 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Thomas Fleming
bb2d433971 Fix mmu lint errors 2021-04-13 19:19:58 -04:00
Thomas Fleming
a545dcb9ae Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-13 17:15:10 -04:00
Katherine Parry
e075dc2d13 Various bugs fixed in FMA 2021-04-13 18:27:13 +00:00
Thomas Fleming
ae888b5705 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
f0c926cf68 Move InstrPageFault to fetch stage 2021-04-13 13:39:22 -04:00
Thomas Fleming
08a84048b6 Add lru algorithm to TLB 2021-04-13 13:37:24 -04:00
Teo Ene
0bffac2c74 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Jarred Allen
95ad9a93a4 Merge branch 'main' into cache 2021-04-13 01:10:03 -04:00
Jarred Allen
357aed75ee A few more cache fixes 2021-04-13 01:07:40 -04:00
Ross Thompson
cb52820249 Fixed minor bug in muldiv which corrects the lint error. 2021-04-09 10:56:31 -05:00
Jarred Allen
6ce4d44ae1 Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Katherine Parry
08f45eb076 fixed FPU lint warnings 2021-04-08 18:03:21 +00:00
Katherine Parry
ebf4915440 fixed FPU lint warnings 2021-04-08 17:55:25 +00:00
Domenico Ottolia
1bdfac6a77 Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
bd310a55af Refactor TLB into multiple files 2021-04-08 03:24:10 -04:00
Thomas Fleming
b3795cef2e Provide attribution link for priority encoder 2021-04-08 03:05:06 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
7f12c7af90 Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
Ross Thompson
d901cfc848 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
a5dc175ab2 Merge remote-tracking branch 'refs/remotes/origin/tests' into tests 2021-04-06 21:20:55 -05:00
Jarred Allen
4da2688c40 Fix another bug in icache 2021-04-06 17:47:00 -04:00
Jarred Allen
ecb2bc8163 Fix another bug in icache 2021-04-06 12:48:42 -04:00
bbracker
80a67dc906 declare memread signal 2021-04-05 08:13:01 -04:00
bbracker
eca92041e9 PLIC claim reg side effects now check for memread signal 2021-04-05 08:03:14 -04:00
bbracker
8f4da826fb plic subword access compliance 2021-04-04 23:10:33 -04:00
Katherine Parry
f41b5a2d38 Added missing files in FPU 2021-04-04 18:09:13 +00:00
bbracker
ce7b2314ef Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
5946b860ca Comment out fpu from hart until module exists 2021-04-03 22:34:11 -04:00
Thomas Fleming
8f31e00f6a Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Thomas Fleming
e04ad8f304 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Jarred Allen
4ebc991a65 Fix bug in icache 2021-04-03 18:10:54 -04:00
Katherine Parry
08b31f7b2a Integrated FPU 2021-04-03 20:52:26 +00:00
Ross Thompson
a743acd1fd Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
James E. Stine
e38e7aff8e Minor cleanup 2021-04-02 08:20:44 -05:00
James E. Stine
9026357350 Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
14cf331265 Merge branch 'main' into mmu 2021-04-01 16:29:39 -04:00
Thomas Fleming
06032936bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Jarred Allen
8dc57a7706 Begin changes to direct-mapped cache 2021-04-01 13:55:21 -04:00
Shreya Sanghai
bf3f4ff5b2 fixed minor bugs in localHistory 2021-04-01 13:40:08 -04:00
James E. Stine
59dee5580c Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time. 2021-04-01 12:30:37 -05:00
ShreyaSanghai
e33007e30e added localHistoryPredictor 2021-04-01 22:22:40 +05:30
Shreya Sanghai
65e9747752 fixed bugs in global history to read latest GHRE 2021-03-31 21:56:14 -04:00
Ross Thompson
f1107c5d7b Corrected a number of bugs in the branch predictor. 
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
 2021-03-31 11:54:02 -05:00
Ross Thompson
1e83810450 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
9388a9f28a Disable 'always-on' virtual memory 2021-03-30 22:49:47 -04:00
Thomas Fleming
e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Ross Thompson
a3925505bf fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
6cda818f09 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
85164c7a87 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
Noah Boorstin
606295db2f Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
edaf89e3d1 Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Jarred Allen
c8a88757ab Fix error when reading an instruction that crosses a line boundary 2021-03-25 18:47:23 -04:00
ShreyaSanghai
da4086db79 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
7338ddf853 Remove old icache 2021-03-25 15:46:35 -04:00
Jarred Allen
fa6e6f1724 Works for misaligned instructions not on line boundaries 2021-03-25 15:42:17 -04:00
Jarred Allen
73d4dd8c15 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Brett Mathis
aedc96cd04 FPU Pipeline completed - can begin integration 2021-03-25 13:29:03 -05:00
Jarred Allen
feabcf2d50 Make cache output NOP after a reset 2021-03-25 13:18:30 -04:00
Jarred Allen
fdecd6c56c Clean up some stuff 2021-03-25 13:04:54 -04:00
Jarred Allen
15e786da0b Working for all of rv64i now, but not compressed instructions 2021-03-25 13:02:26 -04:00
Jarred Allen
e8e4e1bee2 rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
08f4ce4438 More progress on icache controller 2021-03-25 13:01:11 -04:00
Jarred Allen
fff70bccbc Begin rewrite of icache module to use a direct-mapped scheme 2021-03-25 13:01:10 -04:00
Jarred Allen
5a86225e1c Fix bug in cache line 2021-03-25 12:59:30 -04:00
Jarred Allen
abedaf62a8 Output NOP instead of BAD when reset 2021-03-25 12:42:48 -04:00
Jarred Allen
2f5d854f87 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/uncore/dtim.sv
 2021-03-25 12:10:26 -04:00
Thomas Fleming
89a2fe5741 Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
4f01aae844 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
d52c71086a added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
ca392225df added 1 tick delay on tim reads 2021-03-25 02:15:28 -04:00
Jarred Allen
9cbdb44728 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
bbracker
6edb055f26 instrfault direspecting stalls bugfix 2021-03-25 00:44:35 -04:00
bbracker
5327dcfcc8 instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
a8b7d7a248 upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
bbracker
3e656fc035 future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
f2604797fb Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Katherine Parry
123e63b440 fixed various bugs in the FMA 2021-03-24 21:51:17 +00:00
Ross Thompson
cdb7d15709 Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions. 2021-03-24 15:56:55 -05:00
Jarred Allen
0776127c75 Give some cache mem inputs a better name 2021-03-24 12:31:50 -04:00
Jarred Allen
abf9f3b3cb Fix compile errors from const not actually being constant (why does Verilog do this) 2021-03-24 00:58:56 -04:00
Ross Thompson
ace39940b4 Fixed RAS errors. Still some room for improvement with the BTB and RAS. 2021-03-23 23:00:44 -05:00
Jarred Allen
1f01a12be9 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Ross Thompson
72d25d4443 Fixed a bunch of bugs with the RAS. 2021-03-23 21:49:16 -05:00
Katherine Parry
fb78dedae2 fixed various bugs in the FMA 2021-03-24 01:35:32 +00:00
Ross Thompson
c318606f05 Fixed the valid bit issue. Now the branch predictor is actually predicting instructions. 2021-03-23 20:20:23 -05:00
Ross Thompson
9d5c351340 fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle. 2021-03-23 20:06:45 -05:00
Ross Thompson
dee5d16850 fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled. 2021-03-23 16:53:48 -05:00
Jarred Allen
ebd2c60b74 Begin work on direct-mapped cache 2021-03-23 17:03:02 -04:00
Teo Ene
8556c07261 Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem 2021-03-23 15:21:13 -05:00
Shreya Sanghai
09b90557f7 PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
34cc9b4aeb Document some internal signals 2021-03-23 00:10:35 -04:00
Jarred Allen
e4ebb4e31e Add comments explaining icache inputs 2021-03-23 00:07:39 -04:00
Jarred Allen
c47a80213e Small commit to see if new hook tests non-main branch 2021-03-22 23:57:01 -04:00
Noah Boorstin
1592332d41 Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
bbracker
c3a6d6bf42 added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
Jarred Allen
307e33bc7e Remove DelaySideD since it isn't needed 2021-03-22 15:13:23 -04:00