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Fixed synthesis bug with icache valid bit.

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Ross Thompson 2021-05-04 13:03:08 -05:00
parent 87d3869a6e
commit 2aa4db470b
1 changed files with 3 additions and 1 deletions
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4
wally-pipelined/src/ifu/icacheMem.sv
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@ -89,7 +89,9 @@ module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, p
// Correctly handle the valid bits
always_ff @(posedge clk, posedge reset) begin
if (reset || flush) begin
if (reset) begin
ValidOut <= {NUMLINES{1'b0}};
end else if (flush) begin
ValidOut <= {NUMLINES{1'b0}};
end else begin
if (WriteEnable) begin