mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-24 05:24:49 +00:00
do script refactor
This commit is contained in:
bbracker
parent
3bf79923d4
commit
5687ab1c96
@ -94,7 +94,8 @@
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`define OVPSIM_CSR_CONFIG 1
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// Hardware configuration
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`define UART_PRESCALE 1
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//`define UART_PRESCALE 1
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`define UART_PRESCALE 0
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// Interrupt configuration
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`define PLIC_NUM_SRC 53
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@ -1 +0,0 @@
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vsim -do wally-peripherals.do
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@ -31,7 +31,7 @@ vlog +incdir+../config/buildroot ../testbench/testbench-busybear.sv ../src/*/*.s
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt work.testbench_busybear -o workopt
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vopt work.testbench -o workopt
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vsim workopt -suppress 8852,12070
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@ -31,136 +31,12 @@ vlog +incdir+../config/buildroot ../testbench/testbench-busybear.sv ../src/*/*.s
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench_busybear -o workopt
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vopt +acc work.testbench -o workopt
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vsim workopt -suppress 8852,12070
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do ./wave-dos/busybear-waves.do
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view wave
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-- display input and output signals as hexidecimal values
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# Diplays All Signals recursively
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add wave /testbench_busybear/clk
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add wave /testbench_busybear/reset
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add wave -divider
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add wave -hex /testbench_busybear/PCtext
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add wave -hex /testbench_busybear/pcExpected
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add wave -hex /testbench_busybear/dut/hart/ifu/PCD
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
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add wave -hex /testbench_busybear/dut/hart/ifu/StallD
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add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
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add wave -hex /testbench_busybear/dut/hart/ifu/StallE
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add wave -hex /testbench_busybear/dut/hart/ifu/FlushE
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
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add wave /testbench_busybear/CheckInstrD
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add wave /testbench_busybear/lastCheckInstrD
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add wave /testbench_busybear/speculative
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add wave /testbench_busybear/lastPC2
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add wave -divider
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add wave -divider
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add wave /testbench_busybear/dut/uncore/HSELBootTim
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add wave /testbench_busybear/dut/uncore/HSELTim
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add wave /testbench_busybear/dut/uncore/HREADTim
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add wave /testbench_busybear/dut/uncore/dtim/HREADTim0
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add wave /testbench_busybear/dut/uncore/HREADYTim
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add wave -divider
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add wave /testbench_busybear/dut/uncore/HREADBootTim
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add wave /testbench_busybear/dut/uncore/bootdtim/HREADTim0
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add wave /testbench_busybear/dut/uncore/HREADYBootTim
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add wave /testbench_busybear/dut/uncore/HADDR
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add wave /testbench_busybear/dut/uncore/HRESP
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add wave /testbench_busybear/dut/uncore/HREADY
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add wave /testbench_busybear/dut/uncore/HRDATA
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIE_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIDELEG_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MEDELEG_REG
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add wave -divider
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# registers!
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add wave -hex /testbench_busybear/regExpected
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add wave -hex /testbench_busybear/regNumExpected
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add wave -hex /testbench_busybear/HWRITE
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add wave -hex /testbench_busybear/dut/hart/MemRWM[1]
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add wave -hex /testbench_busybear/HWDATA
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add wave -hex /testbench_busybear/HRDATA
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add wave -hex /testbench_busybear/HADDR
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add wave -hex /testbench_busybear/readAdrExpected
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[1]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[2]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[3]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[4]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[5]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[6]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[7]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[8]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[9]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[10]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[11]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[12]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[13]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[14]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[15]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[16]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[17]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[18]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[19]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[20]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[21]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[22]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[23]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[24]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[25]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[26]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[27]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[28]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[29]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[30]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[31]
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add wave /testbench_busybear/InstrFName
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add wave -hex /testbench_busybear/dut/hart/ifu/PCD
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#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
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add wave /testbench_busybear/InstrDName
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#add wave -divider
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add wave -hex /testbench_busybear/dut/hart/ifu/PCE
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##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE
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add wave /testbench_busybear/InstrEName
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE
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#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE
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#add wave -divider
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add wave -hex /testbench_busybear/dut/hart/ifu/PCM
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##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM
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add wave /testbench_busybear/InstrMName
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#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite
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#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM
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#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM
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#add wave -divider
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add wave -hex /testbench_busybear/PCW
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##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW
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add wave /testbench_busybear/InstrWName
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#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW
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#add wave -divider
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##add ww
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add wave -hex -r /testbench_busybear/*
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#
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#-- Set Wave Output Items
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#TreeUpdate [SetDefaultTree]
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#WaveRestoreZoom {0 ps} {100 ps}
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#configure wave -namecolwidth 250
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#configure wave -valuecolwidth 120
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#configure wave -justifyvalue left
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#configure wave -signalnamewidth 0
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#configure wave -snapdistance 10
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#configure wave -datasetprefix 0
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#configure wave -rowmargin 4
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#configure wave -childrowmargin 2
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#set DefaultRadix hexadecimal
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#
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#-- Run the Simulation
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run -all
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##quit
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@ -31,7 +31,7 @@ vlog +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt work.testbench_busybear -o workopt
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vopt work.testbench -o workopt
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vsim workopt -suppress 8852,12070
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@ -31,136 +31,12 @@ vlog +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench_busybear -o workopt
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vopt +acc work.testbench -o workopt
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vsim workopt -suppress 8852,12070
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do ./wave-dos/peripheral-waves.do
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view wave
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-- display input and output signals as hexidecimal values
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# Diplays All Signals recursively
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add wave /testbench_busybear/clk
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add wave /testbench_busybear/reset
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add wave -divider
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add wave -hex /testbench_busybear/PCtext
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add wave -hex /testbench_busybear/pcExpected
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add wave -hex /testbench_busybear/dut/hart/ifu/PCD
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
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add wave -hex /testbench_busybear/dut/hart/ifu/StallD
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add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
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add wave -hex /testbench_busybear/dut/hart/ifu/StallE
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add wave -hex /testbench_busybear/dut/hart/ifu/FlushE
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
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add wave /testbench_busybear/CheckInstrD
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add wave /testbench_busybear/lastCheckInstrD
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add wave /testbench_busybear/speculative
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add wave /testbench_busybear/lastPC2
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add wave -divider
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add wave -divider
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add wave /testbench_busybear/dut/uncore/HSELBootTim
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add wave /testbench_busybear/dut/uncore/HSELTim
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add wave /testbench_busybear/dut/uncore/HREADTim
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add wave /testbench_busybear/dut/uncore/dtim/HREADTim0
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add wave /testbench_busybear/dut/uncore/HREADYTim
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add wave -divider
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add wave /testbench_busybear/dut/uncore/HREADBootTim
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add wave /testbench_busybear/dut/uncore/bootdtim/HREADTim0
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add wave /testbench_busybear/dut/uncore/HREADYBootTim
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add wave /testbench_busybear/dut/uncore/HADDR
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add wave /testbench_busybear/dut/uncore/HRESP
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add wave /testbench_busybear/dut/uncore/HREADY
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add wave /testbench_busybear/dut/uncore/HRDATA
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIE_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIDELEG_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MEDELEG_REG
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add wave -divider
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# registers!
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add wave -hex /testbench_busybear/regExpected
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add wave -hex /testbench_busybear/regNumExpected
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add wave -hex /testbench_busybear/HWRITE
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add wave -hex /testbench_busybear/dut/hart/MemRWM[1]
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add wave -hex /testbench_busybear/HWDATA
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add wave -hex /testbench_busybear/HRDATA
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add wave -hex /testbench_busybear/HADDR
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add wave -hex /testbench_busybear/readAdrExpected
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[1]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[2]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[3]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[4]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[5]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[6]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[7]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[8]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[9]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[10]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[11]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[12]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[13]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[14]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[15]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[16]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[17]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[18]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[19]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[20]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[21]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[22]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[23]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[24]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[25]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[26]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[27]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[28]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[29]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[30]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[31]
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add wave /testbench_busybear/InstrFName
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add wave -hex /testbench_busybear/dut/hart/ifu/PCD
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#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
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add wave /testbench_busybear/InstrDName
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#add wave -divider
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add wave -hex /testbench_busybear/dut/hart/ifu/PCE
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##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE
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add wave /testbench_busybear/InstrEName
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE
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#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE
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#add wave -divider
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add wave -hex /testbench_busybear/dut/hart/ifu/PCM
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##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM
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add wave /testbench_busybear/InstrMName
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#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite
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#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM
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#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM
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#add wave -divider
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add wave -hex /testbench_busybear/PCW
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##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW
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add wave /testbench_busybear/InstrWName
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#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW
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#add wave -divider
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##add ww
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add wave -hex -r /testbench_busybear/*
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#
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#-- Set Wave Output Items
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#TreeUpdate [SetDefaultTree]
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#WaveRestoreZoom {0 ps} {100 ps}
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#configure wave -namecolwidth 250
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#configure wave -valuecolwidth 120
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#configure wave -justifyvalue left
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#configure wave -signalnamewidth 0
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#configure wave -snapdistance 10
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#configure wave -datasetprefix 0
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#configure wave -rowmargin 4
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#configure wave -childrowmargin 2
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#set DefaultRadix hexadecimal
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#
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#-- Run the Simulation
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run -all
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##quit
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@ -40,20 +40,7 @@ vsim workopt
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view wave
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-- display input and output signals as hexidecimal values
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do ./wave-dos/peripheral-waves.do
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-- Set Wave Output Items
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TreeUpdate [SetDefaultTree]
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WaveRestoreZoom {0 ps} {100 ps}
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 120
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
do ./wave-dos/default-waves.do
|
||||
|
||||
-- Run the Simulation
|
||||
#run 5000
|
||||
|
||||
@ -1,3 +1,7 @@
|
||||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
@ -94,3 +98,16 @@ add wave -hex /testbench/dut/uncore/dtim/*
|
||||
add wave -divider
|
||||
|
||||
add wave -hex -r /testbench/*
|
||||
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {100 ps}
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 150
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
@ -1,3 +1,8 @@
|
||||
# ahb-waves.do
|
||||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
@ -78,3 +83,16 @@ add wave -hex /testbench/dut/uncore/dtim/*
|
||||
add wave -divider
|
||||
|
||||
add wave -hex -r /testbench/*
|
||||
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {100 ps}
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 150
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
128
wally-pipelined/regression/wave-dos/busybear-waves.do
Normal file
128
wally-pipelined/regression/wave-dos/busybear-waves.do
Normal file
@ -0,0 +1,128 @@
|
||||
# busybear-waves.do
|
||||
|
||||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
add wave -hex /testbench/PCtext
|
||||
add wave -hex /testbench/pcExpected
|
||||
add wave -hex /testbench/dut/hart/ifu/PCD
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrD
|
||||
add wave -hex /testbench/dut/hart/ifu/StallD
|
||||
add wave -hex /testbench/dut/hart/ifu/FlushD
|
||||
add wave -hex /testbench/dut/hart/ifu/StallE
|
||||
add wave -hex /testbench/dut/hart/ifu/FlushE
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrRawD
|
||||
add wave /testbench/CheckInstrD
|
||||
add wave /testbench/lastCheckInstrD
|
||||
add wave /testbench/speculative
|
||||
add wave /testbench/lastPC2
|
||||
add wave -divider
|
||||
add wave -divider
|
||||
add wave /testbench/dut/uncore/HSELBootTim
|
||||
add wave /testbench/dut/uncore/HSELTim
|
||||
add wave /testbench/dut/uncore/HREADTim
|
||||
add wave /testbench/dut/uncore/dtim/HREADTim0
|
||||
add wave /testbench/dut/uncore/HREADYTim
|
||||
add wave -divider
|
||||
add wave /testbench/dut/uncore/HREADBootTim
|
||||
add wave /testbench/dut/uncore/bootdtim/HREADTim0
|
||||
add wave /testbench/dut/uncore/HREADYBootTim
|
||||
add wave /testbench/dut/uncore/HADDR
|
||||
add wave /testbench/dut/uncore/HRESP
|
||||
add wave /testbench/dut/uncore/HREADY
|
||||
add wave /testbench/dut/uncore/HRDATA
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/MTVEC_REG
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/MSTATUS_REG
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/SCOUNTEREN_REG
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/MIE_REG
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/MIDELEG_REG
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/MEDELEG_REG
|
||||
add wave -divider
|
||||
# registers!
|
||||
add wave -hex /testbench/regExpected
|
||||
add wave -hex /testbench/regNumExpected
|
||||
add wave -hex /testbench/HWRITE
|
||||
add wave -hex /testbench/dut/hart/MemRWM[1]
|
||||
add wave -hex /testbench/HWDATA
|
||||
add wave -hex /testbench/HRDATA
|
||||
add wave -hex /testbench/HADDR
|
||||
add wave -hex /testbench/readAdrExpected
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[1]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[2]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[3]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[4]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[5]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[6]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[7]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[8]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[9]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[10]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[11]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[12]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[13]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[14]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[15]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[16]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[17]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[18]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[19]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[20]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[21]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[22]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[23]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[24]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[25]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[26]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[27]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[28]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[29]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[30]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[31]
|
||||
add wave /testbench/InstrFName
|
||||
add wave -hex /testbench/dut/hart/ifu/PCD
|
||||
#add wave -hex /testbench/dut/hart/ifu/InstrD
|
||||
add wave /testbench/InstrDName
|
||||
#add wave -divider
|
||||
add wave -hex /testbench/dut/hart/ifu/PCE
|
||||
##add wave -hex /testbench/dut/hart/ifu/InstrE
|
||||
add wave /testbench/InstrEName
|
||||
#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
|
||||
#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
|
||||
#add wave /testbench/dut/hart/ieu/dp/PCSrcE
|
||||
#add wave -divider
|
||||
add wave -hex /testbench/dut/hart/ifu/PCM
|
||||
##add wave -hex /testbench/dut/hart/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
#add wave /testbench/dut/hart/dmem/dtim/memwrite
|
||||
#add wave -hex /testbench/dut/hart/dmem/AdrM
|
||||
#add wave -hex /testbench/dut/hart/dmem/WriteDataM
|
||||
#add wave -divider
|
||||
add wave -hex /testbench/PCW
|
||||
##add wave -hex /testbench/dut/hart/ifu/InstrW
|
||||
add wave /testbench/InstrWName
|
||||
#add wave /testbench/dut/hart/ieu/dp/RegWriteW
|
||||
#add wave -hex /testbench/dut/hart/ieu/dp/ResultW
|
||||
#add wave -hex /testbench/dut/hart/ieu/dp/RdW
|
||||
#add wave -divider
|
||||
##add ww
|
||||
add wave -hex -r /testbench/*
|
||||
#
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {100 ps}
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 150
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
@ -1,4 +1,8 @@
|
||||
# These were ripped from wally-pipelined.do
|
||||
# default-waves.do
|
||||
|
||||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
# Diplays All Signals recursively
|
||||
add wave /testbench/clk
|
||||
@ -53,3 +57,16 @@ add wave -hex /testbench/dut/hart/ieu/dp/RdW
|
||||
add wave -divider
|
||||
#add ww
|
||||
add wave -hex -r /testbench/*
|
||||
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {100 ps}
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 150
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
@ -1,10 +1,4 @@
|
||||
# wally-peripherals-signals.do
|
||||
#
|
||||
# Created by Ben Bracker (bbracker@hmc.edu) on 4 Mar. 2021
|
||||
#
|
||||
# I really didn't like having to relaunch and recompile an entire sim
|
||||
# just because some signal names have changed, so I thought this
|
||||
# would be good to factor out.
|
||||
# peripheral-waves.do
|
||||
|
||||
restart -f
|
||||
delete wave /*
|
||||
@ -58,14 +52,14 @@ add wave -divider
|
||||
add wave -divider
|
||||
|
||||
# peripherals
|
||||
add wave -hex /testbench/dut/uncore/uart/u/*
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/uncore/gpio/*
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/uncore/plic/*
|
||||
add wave -hex /testbench/dut/uncore/plic/intPriority
|
||||
add wave -hex /testbench/dut/uncore/plic/pendingArray
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/uncore/uart/u/*
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/hart/ebu/*
|
||||
add wave -divider
|
||||
add wave -divider
|
||||
@ -73,3 +67,15 @@ add wave -divider
|
||||
# everything else
|
||||
add wave -hex -r /testbench/*
|
||||
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {100 ps}
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 150
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
@ -22,7 +22,7 @@ module booth(xExt, choose, add1, e, pp);
|
||||
3'b100 : pp = {negx, 1'b0}; // -2
|
||||
3'b101 : pp = {1'b1, negx}; // -1
|
||||
3'b110 : pp = {1'b1, negx}; // -1
|
||||
3'b111 : pp = 55'hfffffffffffffff; // -0
|
||||
3'b111 : pp = 55'h7fffffffffffff; // -0
|
||||
endcase
|
||||
|
||||
always_comb
|
||||
|
||||
@ -77,7 +77,6 @@ module plic (
|
||||
|
||||
// account for subword read/write circuitry
|
||||
// -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
|
||||
// *** add ld, sd functionality
|
||||
generate
|
||||
if (`XLEN == 64) begin
|
||||
always_comb
|
||||
@ -102,7 +101,7 @@ module plic (
|
||||
always @(posedge HCLK,negedge HRESETn) begin
|
||||
// resetting
|
||||
if (~HRESETn) begin
|
||||
intPriority <= #1 '{default:3'b0}; // *** does this initialization synthesize cleanly?
|
||||
intPriority <= #1 '{default:3'b0};
|
||||
intEn <= #1 {N{1'b0}};
|
||||
intThreshold <= #1 3'b0;
|
||||
intInProgress <= #1 {N{1'b0}};
|
||||
|
||||
@ -113,10 +113,10 @@ module uartPC16550D(
|
||||
// Input synchronization: 2-stage synchronizer
|
||||
///////////////////////////////////////////
|
||||
always_ff @(posedge HCLK) begin
|
||||
{SINd, DSRbd, DCDbd, CTSbd, RIbd} <= {SIN, DSRb, DCDb, CTSb, RIb};
|
||||
{SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} :
|
||||
{SINd, DSRbd, DCDbd, CTSbd, RIbd} <= #1 {SIN, DSRb, DCDb, CTSb, RIb};
|
||||
{SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= #1 loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} :
|
||||
{SINd, DSRbd, DCDbd, CTSbd, RIbd}; // syncrhonized signals, handle loopback testing
|
||||
{DSRb2, DCDb2, CTSb2, RIb2} <= {DSRbsync, DCDbsync, CTSbsync, RIbsync}; // for detecting state changes
|
||||
{DSRb2, DCDb2, CTSb2, RIb2} <= #1 {DSRbsync, DCDbsync, CTSbsync, RIbsync}; // for detecting state changes
|
||||
end
|
||||
|
||||
///////////////////////////////////////////
|
||||
@ -124,43 +124,43 @@ module uartPC16550D(
|
||||
///////////////////////////////////////////
|
||||
always_ff @(posedge HCLK, negedge HRESETn)
|
||||
if (~HRESETn) begin // Table 3 Reset Configuration
|
||||
IER <= 4'b0;
|
||||
FCR <= 8'b0;
|
||||
LCR <= 8'b0;
|
||||
MCR <= 5'b0;
|
||||
LSR <= 8'b01100000;
|
||||
MSR <= 4'b0;
|
||||
DLL <= 8'b0;
|
||||
DLM <= 8'b0;
|
||||
SCR <= 8'b0; // not strictly necessary to reset
|
||||
IER <= #1 4'b0;
|
||||
FCR <= #1 8'b0;
|
||||
LCR <= #1 8'b0;
|
||||
MCR <= #1 5'b0;
|
||||
LSR <= #1 8'b01100000;
|
||||
MSR <= #1 4'b0;
|
||||
DLL <= #1 8'b0;
|
||||
DLM <= #1 8'b0;
|
||||
SCR <= #1 8'b0; // not strictly necessary to reset
|
||||
end else begin
|
||||
if (~MEMWb) begin
|
||||
case (A)
|
||||
3'b000: if (DLAB) DLL <= Din; // else TXHR <= Din; // TX handled in TX register/FIFO section
|
||||
3'b001: if (DLAB) DLM <= Din; else IER <= Din[3:0];
|
||||
3'b010: FCR <= {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
|
||||
3'b011: LCR <= Din;
|
||||
3'b100: MCR <= Din[4:0];
|
||||
3'b101: LSR[6:1] <= Din[6:1]; // recommended only for test, see 8.6.3
|
||||
3'b110: MSR <= Din[3:0];
|
||||
3'b111: SCR <= Din;
|
||||
3'b000: if (DLAB) DLL <= #1 Din; // else TXHR <= #1 Din; // TX handled in TX register/FIFO section
|
||||
3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
|
||||
3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
|
||||
3'b011: LCR <= #1 Din;
|
||||
3'b100: MCR <= #1 Din[4:0];
|
||||
3'b101: LSR[6:1] <= #1 Din[6:1]; // recommended only for test, see 8.6.3
|
||||
3'b110: MSR <= #1 Din[3:0];
|
||||
3'b111: SCR <= #1 Din;
|
||||
endcase
|
||||
end
|
||||
// Line Status Register (8.6.3)
|
||||
LSR[0] <= rxdataready; // Data ready
|
||||
if (RXBR[10]) LSR[1] <= 1; // overrun error
|
||||
if (RXBR[9]) LSR[2] <= 1; // parity error
|
||||
if (RXBR[8]) LSR[3] <= 1; // framing error
|
||||
if (rxbreak) LSR[4] <= 1; // break indicator
|
||||
LSR[5] <= txhremptyintr ; // THRE
|
||||
LSR[6] <= ~txsrfull & txhremptyintr; // TEMT
|
||||
if (rxfifohaserr) LSR[7] <= 1; // any bits in FIFO have error
|
||||
LSR[0] <= #1 rxdataready; // Data ready
|
||||
if (RXBR[10]) LSR[1] <= #1 1; // overrun error
|
||||
if (RXBR[9]) LSR[2] <= #1 1; // parity error
|
||||
if (RXBR[8]) LSR[3] <= #1 1; // framing error
|
||||
if (rxbreak) LSR[4] <= #1 1; // break indicator
|
||||
LSR[5] <= #1 txhremptyintr ; // THRE
|
||||
LSR[6] <= #1 ~txsrfull & txhremptyintr; // TEMT
|
||||
if (rxfifohaserr) LSR[7] <= #1 1; // any bits in FIFO have error
|
||||
|
||||
// Modem Status Register (8.6.8)
|
||||
MSR[0] <= MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send
|
||||
MSR[1] <= MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready
|
||||
MSR[2] <= MSR[2] | (~RIb2 & RIbsync); // Trailing Edge of Ring Indicator
|
||||
MSR[3] <= MSR[3] | DCDb2 ^ DCDbsync; // Delta Data Carrier Detect
|
||||
MSR[0] <= #1 MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send
|
||||
MSR[1] <= #1 MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready
|
||||
MSR[2] <= #1 MSR[2] | (~RIb2 & RIbsync); // Trailing Edge of Ring Indicator
|
||||
MSR[3] <= #1 MSR[3] | DCDb2 ^ DCDbsync; // Delta Data Carrier Detect
|
||||
end
|
||||
|
||||
always_comb
|
||||
@ -186,11 +186,11 @@ module uartPC16550D(
|
||||
///////////////////////////////////////////
|
||||
always_ff @(posedge HCLK, negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
baudcount <= 0;
|
||||
baudpulse <= 0;
|
||||
baudcount <= #1 0;
|
||||
baudpulse <= #1 0;
|
||||
end else begin
|
||||
baudpulse <= (baudcount == {DLM, DLL, {(`UART_PRESCALE){1'b0}}});
|
||||
baudcount <= baudpulse ? 0 : baudcount +1;
|
||||
baudpulse <= #1 (baudcount == {DLM, DLL, {(`UART_PRESCALE){1'b0}}});
|
||||
baudcount <= #1 baudpulse ? 0 : baudcount +1;
|
||||
end
|
||||
assign txbaudpulse = baudpulse;
|
||||
assign BAUDOUTb = ~baudpulse;
|
||||
@ -202,27 +202,27 @@ module uartPC16550D(
|
||||
|
||||
always_ff @(posedge HCLK, negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
rxoversampledcnt <= 0;
|
||||
rxstate <= UART_IDLE;
|
||||
rxbitsreceived <= 0;
|
||||
rxtimeoutcnt <= 0;
|
||||
rxoversampledcnt <= #1 0;
|
||||
rxstate <= #1 UART_IDLE;
|
||||
rxbitsreceived <= #1 0;
|
||||
rxtimeoutcnt <= #1 0;
|
||||
end else begin
|
||||
if (rxstate == UART_IDLE & ~SINsync) begin // got start bit
|
||||
rxstate <= UART_ACTIVE;
|
||||
rxoversampledcnt <= 0;
|
||||
rxbitsreceived <= 0;
|
||||
rxtimeoutcnt <= 0; // reset timeout when new character is arriving
|
||||
rxstate <= #1 UART_ACTIVE;
|
||||
rxoversampledcnt <= #1 0;
|
||||
rxbitsreceived <= #1 0;
|
||||
rxtimeoutcnt <= #1 0; // reset timeout when new character is arriving
|
||||
end else if (rxbaudpulse & (rxstate == UART_ACTIVE)) begin
|
||||
rxoversampledcnt <= rxoversampledcnt + 1; // 16x oversampled counter
|
||||
if (rxcentered) rxbitsreceived <= rxbitsreceived + 1;
|
||||
if (rxbitsreceived == rxbitsexpected) rxstate <= UART_DONE; // pulse rxdone for a cycle
|
||||
rxoversampledcnt <= #1 rxoversampledcnt + 1; // 16x oversampled counter
|
||||
if (rxcentered) rxbitsreceived <= #1 rxbitsreceived + 1;
|
||||
if (rxbitsreceived == rxbitsexpected) rxstate <= #1 UART_DONE; // pulse rxdone for a cycle
|
||||
end else if (rxstate == UART_DONE || rxstate == UART_BREAK) begin
|
||||
if (rxbreak & ~SINsync) rxstate <= UART_BREAK;
|
||||
else rxstate <= UART_IDLE;
|
||||
if (rxbreak & ~SINsync) rxstate <= #1 UART_BREAK;
|
||||
else rxstate <= #1 UART_IDLE;
|
||||
end
|
||||
// timeout counting
|
||||
if (~MEMRb && A == 3'b000 && ~DLAB) rxtimeoutcnt <= 0; // reset timeout on read
|
||||
else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= rxtimeoutcnt+1; // *** not right
|
||||
if (~MEMRb && A == 3'b000 && ~DLAB) rxtimeoutcnt <= #1 0; // reset timeout on read
|
||||
else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // *** not right
|
||||
end
|
||||
|
||||
assign rxcentered = rxbaudpulse && (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE
|
||||
@ -232,8 +232,8 @@ module uartPC16550D(
|
||||
// receive shift register, buffer register, FIFO
|
||||
///////////////////////////////////////////
|
||||
always_ff @(posedge HCLK, negedge HRESETn)
|
||||
if (~HRESETn) rxshiftreg <= 0;
|
||||
else if (rxcentered) rxshiftreg <= {rxshiftreg[8:0], SINsync}; // capture bit
|
||||
if (~HRESETn) rxshiftreg <= #1 9'b000000001; // initialize so that there is a valid stop bit
|
||||
else if (rxcentered) rxshiftreg <= #1 {rxshiftreg[8:0], SINsync}; // capture bit
|
||||
assign rxparitybit = rxshiftreg[1]; // parity, if it exists, in bit 1 when all done
|
||||
assign rxstopbit = rxshiftreg[0];
|
||||
always_comb
|
||||
@ -255,23 +255,23 @@ module uartPC16550D(
|
||||
// receive FIFO and register
|
||||
always_ff @(posedge HCLK, negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
rxfifohead <= 0; rxfifotail <= 0; rxdataready <= 0; RXBR <= 0;
|
||||
rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0;
|
||||
end else begin
|
||||
if (rxstate == UART_DONE) begin
|
||||
RXBR <= {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register
|
||||
RXBR <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register
|
||||
if (fifoenabled) begin
|
||||
rxfifo[rxfifohead] <= {rxoverrunerr, rxparityerr, rxframingerr, rxdata};
|
||||
rxfifohead <= rxfifohead + 1;
|
||||
rxfifo[rxfifohead] <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata};
|
||||
rxfifohead <= #1 rxfifohead + 1;
|
||||
end
|
||||
rxdataready <= 1;
|
||||
rxdataready <= #1 1;
|
||||
end else if (~MEMRb && A == 3'b000 && ~DLAB) begin // reading RBR updates ready / pops fifo
|
||||
if (fifoenabled) begin
|
||||
rxfifotail <= rxfifotail + 1;
|
||||
if (rxfifohead == rxfifotail +1) rxdataready <= 0;
|
||||
end else rxdataready <= 0;
|
||||
rxfifotail <= #1 rxfifotail + 1;
|
||||
if (rxfifohead == rxfifotail +1) rxdataready <= #1 0;
|
||||
end else rxdataready <= #1 0;
|
||||
end else if (~MEMWb && A == 3'b010) // writes to FIFO Control Register
|
||||
if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents
|
||||
rxfifohead <= 0; rxfifotail <= 0;
|
||||
rxfifohead <= #1 0; rxfifotail <= #1 0;
|
||||
end
|
||||
end
|
||||
|
||||
@ -298,9 +298,9 @@ module uartPC16550D(
|
||||
|
||||
// receive buffer register and ready bit
|
||||
always_ff @(posedge HCLK, negedge HRESETn) // track rxrdy for DMA mode (FCR3 = FCR0 = 1)
|
||||
if (~HRESETn) rxfifodmaready <= 0;
|
||||
else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= 1;
|
||||
else if (rxfifoempty) rxfifodmaready <= 0;
|
||||
if (~HRESETn) rxfifodmaready <= #1 0;
|
||||
else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= #1 1;
|
||||
else if (rxfifoempty) rxfifodmaready <= #1 0;
|
||||
|
||||
always_comb
|
||||
if (fifoenabled) begin
|
||||
@ -318,21 +318,21 @@ module uartPC16550D(
|
||||
///////////////////////////////////////////
|
||||
always_ff @(posedge HCLK, negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
txoversampledcnt <= 0;
|
||||
txstate <= UART_IDLE;
|
||||
txbitssent <= 0;
|
||||
txoversampledcnt <= #1 0;
|
||||
txstate <= #1 UART_IDLE;
|
||||
txbitssent <= #1 0;
|
||||
end else if ((txstate == UART_IDLE) && txsrfull) begin // start transmitting
|
||||
txstate <= UART_ACTIVE;
|
||||
txoversampledcnt <= 1;
|
||||
txbitssent <= 0;
|
||||
txstate <= #1 UART_ACTIVE;
|
||||
txoversampledcnt <= #1 1;
|
||||
txbitssent <= #1 0;
|
||||
end else if (txbaudpulse & (txstate == UART_ACTIVE)) begin
|
||||
txoversampledcnt <= txoversampledcnt + 1;
|
||||
txoversampledcnt <= #1 txoversampledcnt + 1;
|
||||
if (txnextbit) begin // transmit at end of phase
|
||||
txbitssent <= txbitssent+1;
|
||||
if (txbitssent == txbitsexpected) txstate <= UART_DONE;
|
||||
txbitssent <= #1 txbitssent+1;
|
||||
if (txbitssent == txbitsexpected) txstate <= #1 UART_DONE;
|
||||
end
|
||||
end else if (txstate == UART_DONE) begin
|
||||
txstate <= UART_IDLE;
|
||||
txstate <= #1 UART_IDLE;
|
||||
end
|
||||
|
||||
assign txbitsexpected = 1 + (5 + LCR[1:0]) + LCR[3] + 1 + LCR[2] - 1; // start bit + data bits + (parity bit) + stop bit(s)
|
||||
@ -366,35 +366,35 @@ module uartPC16550D(
|
||||
// registers & FIFO
|
||||
always_ff @(posedge HCLK, negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
txfifohead <= 0; txfifotail <= 0; txhrfull <= 0; txsrfull <= 0; TXHR <= 0; txsr <= 12'hfff;
|
||||
txfifohead <= #1 0; txfifotail <= #1 0; txhrfull <= #1 0; txsrfull <= #1 0; TXHR <= #1 0; txsr <= #1 12'hfff;
|
||||
end else begin
|
||||
if (~MEMWb && A == 3'b000 && ~DLAB) begin // writing transmit holding register or fifo
|
||||
if (fifoenabled) begin
|
||||
txfifo[txfifohead] <= Din;
|
||||
txfifohead <= txfifohead + 1;
|
||||
txfifo[txfifohead] <= #1 Din;
|
||||
txfifohead <= #1 txfifohead + 1;
|
||||
end else begin
|
||||
TXHR <= Din;
|
||||
txhrfull <= 1;
|
||||
TXHR <= #1 Din;
|
||||
txhrfull <= #1 1;
|
||||
end
|
||||
$write("%c",Din); // for testbench
|
||||
end
|
||||
if (txstate == UART_IDLE) begin // move data into tx shift register if available
|
||||
if (fifoenabled) begin
|
||||
if (~txfifoempty) begin
|
||||
txsr <= txdata;
|
||||
txfifotail <= txfifotail+1;
|
||||
txsrfull <= 1;
|
||||
txsr <= #1 txdata;
|
||||
txfifotail <= #1 txfifotail+1;
|
||||
txsrfull <= #1 1;
|
||||
end
|
||||
end else if (txhrfull) begin
|
||||
txsr <= txdata;
|
||||
txhrfull <= 0;
|
||||
txsrfull <= 1;
|
||||
txsr <= #1 txdata;
|
||||
txhrfull <= #1 0;
|
||||
txsrfull <= #1 1;
|
||||
end
|
||||
end else if (txstate == UART_DONE) txsrfull <= 0; // done transmitting shift register
|
||||
else if (txstate == UART_ACTIVE && txnextbit) txsr <= {txsr[10:0], 1'b1}; // shift txhr
|
||||
end else if (txstate == UART_DONE) txsrfull <= #1 0; // done transmitting shift register
|
||||
else if (txstate == UART_ACTIVE && txnextbit) txsr <= #1 {txsr[10:0], 1'b1}; // shift txhr
|
||||
if (!MEMWb && A == 3'b010) // writes to FIFO control register
|
||||
if (Din[2] | ~Din[0]) begin // tx FIFO reste or FIFO disable clears FIFO contents
|
||||
txfifohead <= 0; txfifotail <= 0;
|
||||
txfifohead <= #1 0; txfifotail <= #1 0;
|
||||
end
|
||||
end
|
||||
|
||||
@ -405,9 +405,9 @@ module uartPC16550D(
|
||||
|
||||
// transmit buffer ready bit
|
||||
always_ff @(posedge HCLK, negedge HRESETn) // track txrdy for DMA mode (FCR3 = FCR0 = 1)
|
||||
if (~HRESETn) txfifodmaready <= 0;
|
||||
else if (txfifoempty) txfifodmaready <= 1;
|
||||
else if (txfifofull) txfifodmaready <= 0;
|
||||
if (~HRESETn) txfifodmaready <= #1 0;
|
||||
else if (txfifoempty) txfifodmaready <= #1 1;
|
||||
else if (txfifofull) txfifodmaready <= #1 0;
|
||||
|
||||
always_comb
|
||||
if (fifoenabled & fifodmamodesel) TXRDYb = ~txfifodmaready;
|
||||
@ -440,7 +440,7 @@ module uartPC16550D(
|
||||
intrpending = 0;
|
||||
end
|
||||
end
|
||||
always @(posedge HCLK) INTR <= intrpending; // prevent glitches on interrupt pin
|
||||
always @(posedge HCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin
|
||||
|
||||
///////////////////////////////////////////
|
||||
// modem control logic
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module testbench_busybear();
|
||||
module testbench();
|
||||
|
||||
logic clk, reset;
|
||||
logic [31:0] GPIOPinsIn;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user