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645 Commits

Author SHA1 Message Date
David Harris
690e2b7f31 Restored counter events 2021-06-10 11:18:58 -04:00
David Harris
0e4e091a39 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-10 10:47:55 -04:00
David Harris
c3d106f0f0 Removed two cycles of latency from the DTIM 2021-06-10 10:30:24 -04:00
bbracker
9c3cb0d2bf peripheral lint fixes 2021-06-10 10:19:10 -04:00
bbracker
f0266f621b merge 2021-06-10 10:03:01 -04:00
bbracker
58d0e46d02 UART improved and added more reg read side effects 2021-06-10 09:53:48 -04:00
David Harris
17b76d4cd7 Configurable number of performance counters 2021-06-10 09:41:26 -04:00
David Harris
6dcf86948c Restored PCCorrectE declaration in IFU 2021-06-09 21:09:16 -04:00
David Harris
e231fc6b00 More verilator fixes, but bpred is broken 2021-06-09 21:03:03 -04:00
David Harris
9dd3857c26 Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
David Harris
9a17556de4 Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00
David Harris
cfe5c27946 Resized BOOT TIM to 1 KB 2021-06-08 14:04:32 -04:00
Kip Macsai-Goren
6ed96761b6 Merge small mmu changes into main 2021-06-08 14:00:26 -04:00
Kip Macsai-Goren
be99c18002 making mmu branch line up with main 2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
41ceb20296 some cleanup of signals, not done yet 2021-06-08 13:39:32 -04:00
bbracker
17960a6484 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine 2021-06-08 12:41:25 -04:00
bbracker
5026a42fac * GPIO comprehensive testing 
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
 2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
e044f72e59 remove redundant decodes, fixed mmu logic ins/outs 2021-06-07 19:23:30 -04:00
Kip Macsai-Goren
146ed95bdb got rid of some underscores in filenames, modules 2021-06-07 18:54:05 -04:00
Kip Macsai-Goren
46b2b19792 implemented simpler page mixers, cleaned up a bit 2021-06-07 18:32:34 -04:00
Kip Macsai-Goren
55d50f5607 began updating cam line to reduce muxes, confusion 2021-06-07 17:03:31 -04:00
Kip Macsai-Goren
1377680270 regression working partially done page mask 2021-06-07 17:02:31 -04:00
David Harris
4740ef97d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-07 16:14:13 -04:00
David Harris
c3d21967f8 Simplified superpage matching 2021-06-07 16:11:28 -04:00
Katherine Parry
b55798f09b lint is clean 2021-06-07 14:22:54 -04:00
David Harris
b37bcc8e38 Continued merge 2021-06-07 12:49:47 -04:00
David Harris
1e67db2f0c Second attept to commit refactoring config files 2021-06-07 12:37:46 -04:00
David Harris
95cc70295b Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Katherine Parry
e4db6ea6f5 fixed lint warnings for fpu and lzd 2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
d69501c4fa Cleaned up some unused signals 2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
b99b5f8e0e moved privilege dfinitions into wally-constants, upgraded relevant includes 2021-06-04 17:55:07 -04:00
Kip Macsai-Goren
4a00fbaf04 Merge branch 'mmu' into main 
new mmu unit and moving pmp/pma now passes regression except for lint and buildroot
 2021-06-04 17:07:56 -04:00
Kip Macsai-Goren
7e41b17e65 restructured so that pma/pmp are a part of mmu 2021-06-04 17:05:07 -04:00
Ross Thompson
6f58c66be8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-04 15:16:39 -05:00
Ross Thompson
e200b4b5a4 Continued I-Cache cleanup. 
Removed strange mux on InstrRawD along with
the select logic.
 2021-06-04 15:14:05 -05:00
Ross Thompson
35afdecda2 Moved I-Cache offset selection mux to icache.sv (top level). 
When we switch to set associative this is will be more efficient.
 2021-06-04 13:49:33 -05:00
Ross Thompson
fdc7c673dd Cleaned up the I-Cache memory. 2021-06-04 13:36:06 -05:00
Katherine Parry
19116ed889 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Ross Thompson
2c16591396 Reorganized the icache names. 2021-06-04 12:53:42 -05:00
Ross Thompson
147be536f1 Relocated the icache to the cache directoy. 2021-06-04 12:23:46 -05:00
David Harris
b836679ae1 Started MMU 2021-06-04 11:59:14 -04:00
David Harris
a61411995a moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
bbracker
d8913e5547 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-03 10:03:26 -04:00
bbracker
8338b3bd34 expanded GPIO testing and caught small GPIO bug 2021-06-03 10:03:09 -04:00
Ross Thompson
db2a38c300 Fixed a few lint errors, 
clock gater was wrong,
missing signal definitions in branch predictor.
 2021-06-02 09:33:24 -05:00
bbracker
4f03ecb6ec Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-02 10:03:23 -04:00
bbracker
28abd28b1f fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
Kip Macsai-Goren
f7deda0514 implemented Sv48. 2021-06-01 17:50:37 -04:00
James E. Stine
7f5e5287b0 delete div.bak 2021-06-01 17:39:54 -04:00
Ross Thompson
2093e7cce3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 15:20:37 -05:00
Ross Thompson
7afbd8d877 The clock gater was not implemented correctly. Now it is level sensitive to a low clock. 2021-06-01 15:05:22 -05:00
James E. Stine
2c140679e3 Minor cosmetic update to fpu.sv 2021-06-01 15:45:32 -04:00
James E. Stine
bccdd2c137 Updates to muldiv.sv for 32-bit div/rem 2021-06-01 15:31:07 -04:00
Ross Thompson
8e330367ac added clock gater to floating point divider to speed up simulation time. 2021-06-01 13:46:21 -05:00
Ross Thompson
605ceb7ddb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 12:42:21 -05:00
Ross Thompson
f5aa5d7c67 Forgot to include the new gshare predictor file. 2021-06-01 12:42:03 -05:00
Kip Macsai-Goren
8f7e69715d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-01 13:20:39 -04:00
Ross Thompson
8f9680556f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346 Now have global history working correctly. 2021-06-01 10:57:43 -05:00
James E. Stine
927aec34a2 Modify muldiv.sv to handle W instructions for 64-bits 2021-05-31 23:27:42 -04:00
Ross Thompson
1db8d0e59c may have fixed the global branch history predictor. 
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
 2021-05-31 16:11:12 -05:00
Kip Macsai-Goren
42af5f9818 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-31 11:01:15 -04:00
James E. Stine
a71b97e878 Cosmetic changes on integer divider 2021-05-31 09:16:30 -04:00
James E. Stine
2f365a9e07 Add enhancements to integer divider including: 
- better comments
  - optimize FSM to end earlier
  - passes for 32-bit or 64-bit depending on parameter to intdiv

Left div.bak in just in case have to revert back to original for now.
 2021-05-31 09:12:21 -04:00
James E. Stine
889b935630 Modify elements of generics for LZD and shifter wrote for integer 
divider.
 2021-05-31 08:36:19 -04:00
bbracker
a45b61ede9 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
Kip Macsai-Goren
529226ac8d made priority encoder parameterizable 2021-05-28 18:09:28 -04:00
Ross Thompson
40bdcda32d It's a bit sloppy, but the global history predictor is working correctly now. 
There were two major bugs with the predictor.
First the update mechanism was completely wrong.  The PHT is updated with the GHR that was used to lookup the prediction.  PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted.  This is important so that back to back branches' GHRs are not the same.  The must be different to avoid aliasing.  Speculation of the GHR update allows them to be different.  On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed.  Updates to follow.
 2021-05-27 23:06:28 -05:00
Katherine Parry
0646e08609 classify unit created and passes imperas tests 2021-05-27 18:53:55 -04:00
Katherine Parry
65eca433b6 All compare instructions pass imperas tests 2021-05-27 15:23:28 -04:00
Katherine Parry
bd05de0dbb FADD and FSUB imperas tests pass 2021-05-26 12:33:33 -04:00
James E. Stine
e3b3321f91 delete old file for FPregfile 2021-05-26 09:13:09 -05:00
James E. Stine
cc2a7ced7f Add regression test for fpadd 2021-05-26 09:12:37 -05:00
Katherine Parry
3869a73a9c renamed top level FPU wires 2021-05-25 20:04:34 -04:00
Ross Thompson
735e511073 fixed bug with icache miss spill fsm branch. 2021-05-25 14:26:22 -05:00
James E. Stine
e32e812f6a Update FPregfile to use more compact code and better structure for ease in reading 2021-05-25 13:21:59 -05:00
Ross Thompson
aa9a81b760 Merge remote-tracking branch 'refs/remotes/origin/main' into main 2021-05-24 23:25:36 -05:00
Ross Thompson
13034c7406 Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF. 2021-05-24 23:24:54 -05:00
James E. Stine
bbc1dfb309 Minor cosmetic elements on div.sv 2021-05-24 19:30:28 -05:00
James E. Stine
1704fdc877 Mod for DIV/REM instruction and update to div.sv unit 2021-05-24 19:29:13 -05:00
Ross Thompson
3c5e87d6c2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-24 14:28:41 -05:00
Katherine Parry
03aea055fa FMV.X.D imperas test passes 2021-05-24 14:44:30 -04:00
Ross Thompson
dd26b754eb Fixed minor bug in instruction class decoding. 2021-05-24 13:41:14 -05:00
Ross Thompson
b06fda88ff Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link). 2021-05-24 12:37:16 -05:00
James E. Stine
194c32defa Update header for FPadd 2021-05-24 08:28:16 -05:00
Katherine Parry
55f22979ca FSD and FLD imperas tests pass 2021-05-23 18:33:14 -04:00
Katherine Parry
71e4a10efb FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
bbracker
8554f2f3cd plic implementation optimizations 2021-05-19 18:10:48 +00:00
Katherine Parry
409438bc95 floating point infinite loop removed from imperas tests 2021-05-18 10:42:51 -04:00
James E. Stine
49cc330bd9 Forgot initialization config for div - apologies 2021-05-17 17:12:27 -05:00
James E. Stine
96eca3287f Add 32/64-bit shifter for update to shifter block 2021-05-17 17:02:13 -05:00
James E. Stine
97cbdae674 Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
Thomas Fleming
fda439b51e Fix comment 2021-05-14 08:06:07 -04:00
Thomas Fleming
1fc607b399 Remove busy-mmu and fix missing signal 2021-05-14 07:14:20 -04:00
Thomas Fleming
980c00fa64 Clean up MMU code 2021-05-14 07:12:32 -04:00
Thomas Fleming
1e0a5ef807 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 15:22:21 -04:00
bbracker
535046e494 small synthesis fixes 2021-05-04 15:21:01 -04:00
Thomas Fleming
37bba95500 Fix compiler warning in PMP checker 2021-05-04 15:18:08 -04:00
Ross Thompson
2aa4db470b Fixed synthesis bug with icache valid bit. 2021-05-04 13:03:08 -05:00
Ross Thompson
87d3869a6e Fixed icache pcmux control for handling miss spill miss. 2021-05-04 11:05:01 -05:00
Thomas Fleming
dac07e34cf Fix bug in PMP checker 
Now we only enforce PMP regions if at least one is non-null
 2021-05-04 03:14:07 -04:00
Thomas Fleming
d7fa0903bc Disable PMP checker to fix test loops 
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
 2021-05-04 01:56:05 -04:00
Thomas Fleming
d53afc8510 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Domenico Ottolia
a7e89f43c1 Fix bug with IllegalInstrFaultM not getting correct value 2021-05-03 22:48:03 -04:00
Thomas Fleming
f78f2b3b5d Adjust attributes in PMA checker 2021-05-03 21:58:32 -04:00
David Harris
96e90402c5 Rolled back fflush on uart. Use -syncio in Modelsim command line instead. 2021-05-03 20:04:44 -04:00
David Harris
062120f944 Flush uart print statements on \n 2021-05-03 19:51:51 -04:00
David Harris
743011194b Flush uart print statements on \n 2021-05-03 19:41:37 -04:00
David Harris
8758b6efa1 Flush uart print statements on \n 2021-05-03 19:37:45 -04:00
David Harris
2f5649832a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:29:01 -04:00
David Harris
1f2da4c457 Flush uart print statements on \n 2021-05-03 19:25:28 -04:00
Ross Thompson
6a01ea9f2d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 16:57:36 -05:00
Ross Thompson
ed4f2ecb24 fixed subtle typo in icache fsm. Was messing up hit spill hit. 
I believe the mibench qsort benchmark runs after this icache fix.
 2021-05-03 16:55:36 -05:00
Domenico Ottolia
ab68933466 Fix bug that caused stvec to get the wrong value 2021-05-03 17:54:57 -04:00
Thomas Fleming
3f7061d557 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 17:38:13 -04:00
Thomas Fleming
86a93d77b4 Implement PMP checker and revise PMA checker 2021-05-03 17:37:42 -04:00
Thomas Fleming
00c3b5a033 Remove remnants of InstrReadC 2021-05-03 17:36:25 -04:00
Ross Thompson
0a44d4dd4e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 14:53:54 -05:00
Ross Thompson
e09ac73eaf Removed combinational loops between icache and PMA checker. 2021-05-03 14:51:25 -05:00
Ross Thompson
7185905f7b Reduced icache to 1 port memory. 2021-05-03 14:47:49 -05:00
Katherine Parry
3f05e31954 fpu warnings fixed/commented 2021-05-03 19:17:09 +00:00
Thomas Fleming
94d734cca9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-05-03 14:02:19 -04:00
Ross Thompson
12b978fec2 Eliminated extra register and fixed ports to icache. 
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
 2021-05-03 12:04:54 -05:00
bbracker
8ec0d18444 merge conflict resolved -- Ross and I made the same fix 2021-05-03 10:10:42 -04:00
Ross Thompson
b57c187208 Fixed typo in ifu for bypassing branch predictor. 
Fixed missing signal name in local history predictor.
 2021-05-03 08:56:45 -05:00
David Harris
c9806fb472 Fixed lint error in div 2021-05-03 09:26:12 -04:00
bbracker
fb0910d9c0 ifu lint fixes 2021-05-03 09:25:22 -04:00
bbracker
acd99be7f8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 09:23:52 -04:00
Katherine Parry
9252d08b41 fpu imperas tests run 2021-05-01 02:18:01 +00:00
bbracker
0d62440f60 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-30 06:26:35 -04:00
bbracker
9c08ce5359 rv32 plic test and lint fixes 2021-04-30 06:26:31 -04:00
Domenico Ottolia
830787e3e1 Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts 2021-04-29 20:42:14 -04:00
Thomas Fleming
10c7260980 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-29 16:30:00 -04:00
ushakya22
de23edcfb9 fix to pcm bug 2021-04-29 15:21:08 -04:00
Jarred Allen
000f48cd75 Fix compile error in branch predictor 2021-04-29 14:36:56 -04:00
Shreya Sanghai
b554dc8e72 fixed bug in gshare, global and local history BP 2021-04-29 06:14:32 -04:00
Thomas Fleming
e091f430e0 Clean up PMA checker and begin PMP checker 2021-04-29 02:20:39 -04:00
Ross Thompson
14a69c1d06 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Ross Thompson
a7e4d39ea1 Fixed issue with not saving the first cache block read on a miss spill. 2021-04-26 12:57:34 -05:00
Ross Thompson
44d28dbd1c Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
bbracker
f921886451 merge cleanup; mem init is broken 2021-04-26 08:00:17 -04:00
bbracker
7947858481 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
8d77012995 progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
46a1616079 thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
5687ab1c96 do script refactor 2021-04-24 09:32:09 -04:00
Thomas Fleming
6f23858609 Fix HSIZE and HBURST signal widths in PMA checker 2021-04-23 20:11:43 -04:00
Ross Thompson
d7fea1ba3c almost working icache. 2021-04-23 16:47:23 -05:00
Ross Thompson
c9bdaceddb Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Ross Thompson
04eb302925 Yes. The hack to not repeat the d memory operation fixed this issue. 2021-04-22 15:22:56 -05:00
Thomas Fleming
5bff582608 Write PCM to TVAL registers 2021-04-22 16:17:57 -04:00
Thomas Fleming
07770a46d8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 15:37:19 -04:00
Thomas Fleming
74fb1dccad Prepare to squash bad ahb accesses 2021-04-22 15:36:45 -04:00
Thomas Fleming
c055ab272d Clean up lint errors in fpu and muldiv 
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
 2021-04-22 15:36:03 -04:00
Domenico Ottolia
787ae978d7 Fix misa synthesis bug (for real now) 2021-04-22 15:35:20 -04:00
Thomas Fleming
e7822ce20c Implement first pass at the PMA checker 2021-04-22 15:34:02 -04:00
Thomas Fleming
805ac5dbd7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 13:20:12 -04:00
bbracker
c796547156 greatly improved PLIC register interface 2021-04-22 11:22:01 -04:00
Ross Thompson
7c8d2e9b78 Partially working icache. 
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory.  This keeps StallF high and
the icache FSM is never allowed to complete.
 2021-04-22 10:20:36 -05:00
Thomas Fleming
d22f0f9d63 Refactor tlb_ram to use flop primitives 2021-04-22 01:52:43 -04:00
Thomas Fleming
4d4ca24640 Extend stall on leaf page lookups 2021-04-22 01:51:38 -04:00
Domenico Ottolia
939e36a151 Fix misa bug 2021-04-22 00:59:07 -04:00
Thomas Fleming
88bd151d55 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-04-21 20:01:08 -04:00
Thomas Fleming
70c801331a Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Ross Thompson
50e893eec9 Fixed for the instruction spills. 2021-04-21 16:47:05 -05:00
Teo Ene
008b308b79 Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
Ross Thompson
269ea7997c major progress. 
It's running the icache is imperas tests now.
Compressed does not work yet.
 2021-04-21 08:39:54 -05:00
Domenico Ottolia
d5f86fadac Add tests for sepc register 2021-04-20 23:50:53 -04:00
Ross Thompson
a861a37b72 Why was the linter messed up? 
There are a number of combo loops which need fixing outside the icache.  They may be fixed in main.
We get to instruction address 50 now!
 2021-04-20 22:06:12 -05:00
Ross Thompson
daa1ab9261 Progress on icache. Fixed some issues aligning the PC with instruction. Still broken. 2021-04-20 21:19:53 -05:00
Ross Thompson
649589ee2c Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Domenico Ottolia
e02ff60b07 Fix synthesis warnings for privileged unit (replace 'initial' settings) 2021-04-20 17:57:56 -04:00
Jarred Allen
59b340dac9 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Katherine Parry
204e5cb018 fixed synth bugs in fpu 2021-04-19 00:39:16 +00:00
Noah Boorstin
d0a137ce0c neat verilog thing 2021-04-18 17:48:51 -04:00
Jarred Allen
3868a82932 dcache lints 2021-04-15 21:13:56 -04:00
bbracker
11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
a149f2f3d8 Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
Teo Ene
a9c6d357d8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 15:29:09 -05:00
Teo Ene
7a40c27b59 Quick fix to ahblite missing default statement done in class :) 2021-04-15 15:29:04 -05:00
Thomas Fleming
e8770e3eac Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/mmu/priority_encoder.sv
 2021-04-15 16:20:43 -04:00
Thomas Fleming
e838f0bb3d Change priority encoder to avoid extra assignment 2021-04-15 16:17:35 -04:00
Thomas Fleming
2c4682c4be Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Teo Ene
cefc8ea22b Temporary change to mmu/priority_encoder.sv 
Necessary to get synth working
Original HDL is still there, just commented out
 2021-04-15 13:37:12 -05:00
Katherine Parry
0bdd3efdd5 integraded the FMA into the FPU 2021-04-15 18:28:00 +00:00
Jarred Allen
7b4b1a31ef Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Ross Thompson
534e3eaac8 Merge branch 'bpfixes' into main 2021-04-15 09:06:21 -05:00
Shreya Sanghai
75caa65df1 Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
ShreyaSanghai
80fbd66113 added localHistoryPredictor 2021-04-15 08:58:22 -05:00
Shreya Sanghai
3696bf4f2c fixed bugs in global history to read latest GHRE 
Cherry pick Shreya's commits into main branch.
 2021-04-15 08:55:22 -05:00
bbracker
76f50d7a69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 09:06:03 -04:00
bbracker
da22308e60 csri lint improvement 2021-04-15 09:05:53 -04:00
Jarred Allen
4d58f673b2 Add a comment to explain a detail 2021-04-14 23:14:59 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
c32fe09056 More icache bugfixes 2021-04-14 19:03:33 -04:00
Jarred Allen
757b64e487 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00