bbracker 46a1616079 thomas fixed it before I did		2021-04-24 09:38:52 -04:00
..
cache	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
dmem	Implement virtual memory protection	2021-04-21 19:58:36 -04:00
ebu	Fix HSIZE and HBURST signal widths in PMA checker	2021-04-23 20:11:43 -04:00
fpu	do script refactor	2021-04-24 09:32:09 -04:00
generic	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
hazard	Partial fix to the integer divide stall issue.	2021-04-02 15:32:15 -05:00
ieu	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
ifu	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-04-21 20:01:08 -04:00
mmu	Refactor tlb_ram to use flop primitives	2021-04-22 01:52:43 -04:00
muldiv	Clean up lint errors in fpu and muldiv	2021-04-22 15:36:03 -04:00
privileged	Fix HSIZE and HBURST signal widths in PMA checker	2021-04-23 20:11:43 -04:00
uncore	thomas fixed it before I did	2021-04-24 09:38:52 -04:00
wally	Implement first pass at the PMA checker	2021-04-22 15:34:02 -04:00