mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Thomas Fleming
commit
d53afc8510
@ -57,7 +57,8 @@
|
||||
`define MEM_DCACHE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_ICACHE 0
|
||||
`define MEM_VIRTMEM 0
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
@ -85,7 +86,7 @@
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 0
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Busybear special CSR config to match OVPSim
|
||||
`define OVPSIM_CSR_CONFIG 0
|
||||
@ -94,7 +95,10 @@
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 53
|
||||
`define PLIC_NUM_SRC 4
|
||||
//comment out the following if >= 32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 4
|
||||
|
||||
/* verilator lint_off STMTDLY */
|
||||
@ -105,5 +109,5 @@
|
||||
`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE"
|
||||
`define BPTYPE "BPGSHARE"//comments
|
||||
`define TESTSBP 0
|
||||
|
||||
@ -24,11 +24,15 @@
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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||||
///////////////////////////////////////////
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
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||||
`define BUILDROOT 0
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||||
`define BUSYBEAR 0
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||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
//`define MISA (32'h00000104)
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||||
`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20)
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||||
//`define MISA (32'h00000105)
|
||||
`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0)
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||||
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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||||
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
|
||||
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
|
||||
@ -54,7 +58,8 @@
|
||||
`define MEM_DCACHE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_ICACHE 0
|
||||
`define MEM_VIRTMEM 0
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000000000000
|
||||
@ -69,20 +74,20 @@
|
||||
`define BOOTTIMBASE 32'h00800000
|
||||
`define BOOTTIMRANGE 32'h00003FFF
|
||||
`define TIMBASE 32'h00000000
|
||||
`define TIMRANGE 32'h007FFFFF
|
||||
`define CLINTBASE 32'h02000000
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||||
`define CLINTRANGE 32'h0000FFFF
|
||||
`define GPIOBASE 32'h10012000
|
||||
`define GPIORANGE 32'h000000FF
|
||||
`define UARTBASE 32'h10000000
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||||
`define UARTRANGE 32'h00000007
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||||
`define PLICBASE 32'h0C000000
|
||||
`define PLICRANGE 32'h03FFFFFF
|
||||
`define TIMRANGE 32'h07FFFFFF
|
||||
`define CLINTBASE 32'h02000000
|
||||
`define CLINTRANGE 32'h0000FFFF
|
||||
`define GPIOBASE 32'h10012000
|
||||
`define GPIORANGE 32'h000000FF
|
||||
`define UARTBASE 32'h10000000
|
||||
`define UARTRANGE 32'h00000007
|
||||
`define PLICBASE 32'h0C000000
|
||||
`define PLICRANGE 32'h03FFFFFF
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 0
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Busybear special CSR config to match OVPSim
|
||||
`define OVPSIM_CSR_CONFIG 0
|
||||
@ -90,6 +95,13 @@
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 4
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 4
|
||||
|
||||
/* verilator lint_off STMTDLY */
|
||||
/* verilator lint_off WIDTH */
|
||||
/* verilator lint_off ASSIGNDLY */
|
||||
|
||||
@ -26,6 +26,8 @@
|
||||
///////////////////////////////////////////
|
||||
|
||||
// Virtual Memory Constants (sv39)
|
||||
`define VPN_SEGMENT_BITS 9
|
||||
`define VPN_BITS 27
|
||||
`define PPN_BITS 44
|
||||
`define PPN_HIGH_SEGMENT_BITS 26
|
||||
`define PA_BITS 56
|
||||
|
||||
@ -35,6 +35,8 @@ vlog +incdir+../config/coremark_bare ../testbench/testbench-coremark_bare.sv ../
|
||||
vopt +acc work.testbench -o workopt
|
||||
vsim workopt
|
||||
|
||||
mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/RAM
|
||||
|
||||
view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
@ -54,7 +56,7 @@ add wave -divider
|
||||
|
||||
add wave -divider Fetch
|
||||
add wave -hex /testbench/dut/hart/ifu/PCF
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrF
|
||||
add wave -hex /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
|
||||
add wave /testbench/InstrFName
|
||||
add wave -divider Decode
|
||||
add wave -hex /testbench/dut/hart/ifu/PCD
|
||||
@ -90,7 +92,7 @@ add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
|
||||
add wave -divider Regfile_itself
|
||||
add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf
|
||||
add wave -divider RAM
|
||||
add wave -hex -r /testbench/dut/uncore/dtim/RAM
|
||||
#add wave -hex -r /testbench/dut/uncore/dtim/RAM
|
||||
add wave -divider Misc
|
||||
add wave -divider
|
||||
#add wave -hex -r /testbench/*
|
||||
|
||||
@ -1,5 +1,4 @@
|
||||
onerror {resume}
|
||||
quietly virtual function -install /testbench/dut/hart/ifu/icache/cachemem -env /testbench/dut/hart/ifu/icache/cachemem { &{/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[4], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[3], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[2], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[1], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[0] }} offset
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /testbench/clk
|
||||
add wave -noupdate /testbench/reset
|
||||
@ -8,68 +7,68 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPPredF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePC
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdateEN
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePrediction
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
|
||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
|
||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
|
||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
|
||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
|
||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
|
||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
|
||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
|
||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
|
||||
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPPredF
|
||||
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF
|
||||
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF
|
||||
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF
|
||||
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePC
|
||||
add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdateEN
|
||||
add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePrediction
|
||||
add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN
|
||||
add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC
|
||||
add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
|
||||
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE
|
||||
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE
|
||||
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE
|
||||
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE
|
||||
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE
|
||||
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
|
||||
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -expand -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
|
||||
@ -89,18 +88,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
|
||||
add wave -noupdate -group alu -divider internals
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
|
||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
|
||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
|
||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
|
||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
|
||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
|
||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
|
||||
add wave -noupdate -expand -group alu -divider internals
|
||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
|
||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
|
||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
|
||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
|
||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
|
||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
|
||||
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemReadM
|
||||
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemWriteM
|
||||
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemAckW
|
||||
@ -158,9 +157,9 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
|
||||
add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
|
||||
add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
@ -177,28 +176,21 @@ add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/i
|
||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE
|
||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL
|
||||
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LINESIZE
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
|
||||
add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWritePAdr
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadTag
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadAddr
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadPAdr
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WritePAdr
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteSet
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteTag
|
||||
add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
|
||||
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
|
||||
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
|
||||
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
|
||||
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
|
||||
add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
|
||||
add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
|
||||
add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
|
||||
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
|
||||
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
|
||||
add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FlushDLastCyclen
|
||||
@ -223,12 +215,11 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {9951515 ns} 0} {{Cursor 4} {1318991 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 2} {252630976 ns} 1} {{Cursor 4} {72696935 ns} 0} {{Cursor 3} {252631405 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 513
|
||||
configure wave -valuecolwidth 189
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
@ -241,4 +232,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {9951431 ns} {9951599 ns}
|
||||
WaveRestoreZoom {252630882 ns} {252631198 ns}
|
||||
|
||||
@ -216,14 +216,13 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
// Cache fault signals
|
||||
//logic FaultStall;
|
||||
|
||||
//flopenl #(`XLEN) PCPFFlop(clk, reset, SavePC & ~StallF, PCPFinalF, `RESET_VECTOR, PCPF);
|
||||
// on spill we want to get the first 2 bytes of the next cache block.
|
||||
// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
|
||||
// simply add 2 to land on the next cache block.
|
||||
assign PCSpillF = PCPF + 2'b10;
|
||||
|
||||
// now we have to select between these three PCs
|
||||
assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf
|
||||
assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary
|
||||
assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF;
|
||||
|
||||
// this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later.
|
||||
@ -283,7 +282,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
end else if (~hit & ~spill) begin
|
||||
CntReset = 1'b1;
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
end else if (~hit & spill) begin
|
||||
end else if (~hit & spill) begin
|
||||
CntReset = 1'b1;
|
||||
PCMux = 2'b10;
|
||||
NextState = STATE_MISS_SPILL_FETCH_WDV;
|
||||
@ -299,9 +298,10 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
ICacheReadEn = 1'b1;
|
||||
if (hit) begin
|
||||
NextState = STATE_HIT_SPILL_FINAL;
|
||||
end else
|
||||
end else begin
|
||||
CntReset = 1'b1;
|
||||
NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
STATE_HIT_SPILL_MISS_FETCH_WDV: begin
|
||||
PCMux = 2'b10;
|
||||
@ -424,16 +424,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
endcase
|
||||
end
|
||||
|
||||
// fsm outputs
|
||||
// stall CPU any time we are not in the ready state. any other state means the
|
||||
// cache is either requesting data from the memory interface or handling a
|
||||
// spill over two cycles.
|
||||
// *** BUG this logic will need to change
|
||||
//assign ICacheStallF = ((CurrState != STATE_READY) | ~hit | spill) | reset_q ? 1'b1 : 1'b0;
|
||||
// save the PC anytime we are in the ready state. The saved value will be used as the PC may not be stable.
|
||||
//assign SavePC = ((CurrState == STATE_READY) & hit) & ~spill ? 1'b1 : 1'b0;
|
||||
assign CntEn = PreCntEn & InstrAckF;
|
||||
|
||||
assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
|
||||
(CurrState == STATE_MISS_FETCH_WDV) ||
|
||||
(CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
|
||||
@ -456,7 +447,6 @@ module icachecontroller #(parameter LINESIZE = 256) (
|
||||
// we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros.
|
||||
// fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with
|
||||
// more zeros after the addition. This will be the number of offset bits less the AHBByteLength.
|
||||
// *** now a bug need to mux between PCPF and PCPF+2
|
||||
assign InstrPAdrF = {{PCPTrunkF, {{LOGWPL}{1'b0}}} + FetchCount, {{OFFSETWIDTH-LOGWPL}{1'b0}}};
|
||||
|
||||
|
||||
|
||||
@ -146,7 +146,7 @@ module csrm #(parameter
|
||||
assign IllegalCSRMWriteReadonlyM = CSRMWriteM && (CSRAdrM == MVENDORID || CSRAdrM == MARCHID || CSRAdrM == MIMPID || CSRAdrM == MHARTID);
|
||||
|
||||
// CSRs
|
||||
flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, `XLEN'b0, MTVEC_REGW); //busybear: changed reset value to 0
|
||||
flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `XLEN'b0, MTVEC_REGW); //busybear: changed reset value to 0
|
||||
generate
|
||||
if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin // DELEG registers should exist
|
||||
flopenl #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, ZERO, MEDELEG_REGW);
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 9 January 2021
|
||||
// Modified:
|
||||
// dottolia@hmc.edu 3 May 2021 - fix bug with utvec getting wrong value
|
||||
//
|
||||
// Purpose: User-Mode Control and Status Registers for User Mode Exceptions
|
||||
// See RISC-V Privileged Mode Specification 20190608 Table 2.2
|
||||
@ -64,7 +65,7 @@ module csrn #(parameter
|
||||
assign WriteUTVALM = UTrapM | (CSRNWriteM && (CSRAdrM == UTVAL)) && ~StallW;
|
||||
|
||||
// CSRs
|
||||
flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, CSRWriteValM, `RESET_VECTOR, UTVEC_REGW);
|
||||
flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `RESET_VECTOR, UTVEC_REGW);
|
||||
flopenr #(`XLEN) USCRATCHreg(clk, reset, WriteUSCRATCHM, CSRWriteValM, USCRATCH_REGW);
|
||||
flopenr #(`XLEN) UEPCreg(clk, reset, WriteUEPCM, NextEPCM, UEPC_REGW);
|
||||
flopenr #(`XLEN) UCAUSEreg(clk, reset, WriteUCAUSEM, NextCauseM, UCAUSE_REGW);
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 9 January 2021
|
||||
// Modified:
|
||||
// dottolia@hmc.edu 3 May 2021 - fix bug with stvec getting wrong value
|
||||
//
|
||||
// Purpose: Supervisor-Mode Control and Status Registers
|
||||
// See RISC-V Privileged Mode Specification 20190608
|
||||
@ -83,7 +84,7 @@ module csrs #(parameter
|
||||
assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN) && ~StallW;
|
||||
|
||||
// CSRs
|
||||
flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, CSRWriteValM, ZERO, STVEC_REGW); //busybear: change reset to 0
|
||||
flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, ZERO, STVEC_REGW); //busybear: change reset to 0
|
||||
flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
|
||||
flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW);
|
||||
flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, ZERO, SCAUSE_REGW);
|
||||
|
||||
@ -47,7 +47,7 @@ module privdec (
|
||||
assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101);
|
||||
assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001);
|
||||
assign IllegalPrivilegedInstrM = PrivilegedM & ~(uretM|sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
|
||||
assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | IllegalFPUInstrM; // *** generalize this for other instructions
|
||||
assign IllegalInstrFaultM = IllegalIEUInstrFaultM | IllegalFPUInstrM | IllegalPrivilegedInstrM | IllegalCSRAccessM | IllegalFPUInstrM; // *** generalize this for other instructions
|
||||
|
||||
// *** initially, wfi and sfencevma are nop
|
||||
// *** zfenci extension?
|
||||
|
||||
@ -377,7 +377,7 @@ module uartPC16550D(
|
||||
txhrfull <= #1 1;
|
||||
end
|
||||
$write("%c",Din); // for testbench
|
||||
end
|
||||
end
|
||||
if (txstate == UART_IDLE) begin // move data into tx shift register if available
|
||||
if (fifoenabled) begin
|
||||
if (~txfifoempty) begin
|
||||
|
||||
@ -48,7 +48,7 @@ module testbench();
|
||||
|
||||
// pick tests based on modes supported
|
||||
initial
|
||||
tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.memfile", "1000"};
|
||||
tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"};
|
||||
string signame, memfilename;
|
||||
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
|
||||
logic UARTSin, UARTSout;
|
||||
@ -65,7 +65,7 @@ module testbench();
|
||||
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.InstrF,
|
||||
dut.hart.ifu.icache.controller.FinalInstrRawF,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
@ -81,11 +81,12 @@ module testbench();
|
||||
// read test vectors into memory
|
||||
memfilename = tests[0];
|
||||
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
||||
for(j=268437702; j < 268566528; j = j+1)
|
||||
dut.uncore.dtim.RAM[j] = 64'b0;
|
||||
//for(j=268437955; j < 268566528; j = j+1)
|
||||
//dut.uncore.dtim.RAM[j] = 64'b0;
|
||||
// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
|
||||
// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";
|
||||
reset = 1; # 22; reset = 0;
|
||||
//dut.uncore.dtim.RAM[268437713]=64'b1;
|
||||
reset = 1; # 22; reset = 0;
|
||||
end
|
||||
// generate clock to sequence tests
|
||||
always
|
||||
@ -94,7 +95,7 @@ module testbench();
|
||||
end
|
||||
always @(negedge clk)
|
||||
begin
|
||||
if (dut.hart.priv.ebreakM) begin
|
||||
if (dut.hart.priv.ecallM) begin
|
||||
#20;
|
||||
$display("Code ended with ebreakM");
|
||||
$stop;
|
||||
@ -102,8 +103,8 @@ module testbench();
|
||||
end
|
||||
|
||||
initial begin
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -29,15 +29,16 @@
|
||||
module testbench();
|
||||
parameter DEBUG = 0;
|
||||
parameter TESTSBP = 0;
|
||||
parameter TESTSPERIPH = 0 ; // set to 0 for regression
|
||||
localparam MAXSIGLEN = 1000000;
|
||||
parameter TESTSPERIPH = 0; // set to 0 for regression
|
||||
|
||||
logic clk;
|
||||
logic reset;
|
||||
|
||||
parameter SIGNATURESIZE = 5000000;
|
||||
|
||||
int test, i, errors, totalerrors;
|
||||
logic [31:0] sig32[0:MAXSIGLEN];
|
||||
logic [`XLEN-1:0] signature[0:MAXSIGLEN];
|
||||
logic [31:0] sig32[0:SIGNATURESIZE];
|
||||
logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
|
||||
logic [`XLEN-1:0] testadr;
|
||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||
logic [31:0] InstrW;
|
||||
@ -53,71 +54,7 @@ module testbench();
|
||||
|
||||
string tests64f[] = '{
|
||||
"rv64f/I-FADD-S-01", "2000",
|
||||
"rv64f/I-FCLASS-S-01", "2000",
|
||||
"rv64f/I-FCVT-S-L-01", "2000",
|
||||
"rv64f/I-FCVT-S-LU-01", "2000",
|
||||
"rv64f/I-FCVT-S-W-01", "2000",
|
||||
"rv64f/I-FCVT-S-WU-01", "2000",
|
||||
"rv64f/I-FCVT-L-S-01", "2000",
|
||||
"rv64f/I-FCVT-LU-S-01", "2000",
|
||||
"rv64f/I-FCVT-W-S-01", "2000",
|
||||
"rv64f/I-FCVT-WU-S-01", "2000",
|
||||
"rv64f/I-FDIV-S-01", "2000",
|
||||
"rv64f/I-FEQ-S-01", "2000",
|
||||
"rv64f/I-FLE-S-01", "2000",
|
||||
"rv64f/I-FLT-S-01", "2000",
|
||||
"rv64f/I-FMADD-S-01", "2000",
|
||||
"rv64f/I-FMAX-S-01", "2000",
|
||||
"rv64f/I-FMIN-S-01", "2000",
|
||||
"rv64f/I-FMSUB-S-01", "2000",
|
||||
"rv64f/I-FMUL-S-01", "2000",
|
||||
"rv64f/I-FMV-W-X-01", "2000",
|
||||
"rv64f/I-FMV-X-W-01", "2000",
|
||||
"rv64f/I-FNMADD-S-01", "2000",
|
||||
"rv64f/I-FNMSUB-S-01", "2000",
|
||||
"rv64f/I-FSGNJ-S-01", "2000",
|
||||
"rv64f/I-FSGNJN-S-01", "2000",
|
||||
"rv64f/I-FSGNJX-S-01", "2000",
|
||||
"rv64f/I-FSQRT-S-01", "2000",
|
||||
"rv64f/I-FSW-01", "2000",
|
||||
"rv64f/I-FLW-01", "2110",
|
||||
"rv64f/I-FSUB-S-01", "2000"
|
||||
};
|
||||
|
||||
|
||||
string tests64d[] = '{
|
||||
"rv64d/I-FADD-D-01", "2000",
|
||||
"rv64d/I-FCLASS-D-01", "2000",
|
||||
"rv64d/I-FCVT-D-L-01", "2000",
|
||||
"rv64d/I-FCVT-D-LU-01", "2000",
|
||||
"rv64d/I-FCVT-D-S-01", "2000",
|
||||
"rv64d/I-FCVT-D-W-01", "2000",
|
||||
"rv64d/I-FCVT-D-WU-01", "2000",
|
||||
"rv64d/I-FCVT-L-D-01", "2000",
|
||||
"rv64d/I-FCVT-LU-D-01", "2000",
|
||||
"rv64d/I-FCVT-S-D-01", "2000",
|
||||
"rv64d/I-FCVT-W-D-01", "2000",
|
||||
"rv64d/I-FCVT-WU-D-01", "2000",
|
||||
"rv64d/I-FDIV-D-01", "2000",
|
||||
"rv64d/I-FEQ-D-01", "2000",
|
||||
"rv64d/I-FLD-D-01", "2420",
|
||||
"rv64d/I-FLE-D-01", "2000",
|
||||
"rv64d/I-FLT-D-01", "2000",
|
||||
"rv64d/I-FMADD-D-01", "2000",
|
||||
"rv64d/I-FMAX-D-01", "2000",
|
||||
"rv64d/I-FMIN-D-01", "2000",
|
||||
"rv64d/I-FMSUB-D-01", "2000",
|
||||
"rv64d/I-FMUL-D-01", "2000",
|
||||
"rv64d/I-FMV-D-X-01", "2000",
|
||||
"rv64d/I-FMV-X-D-01", "2000",
|
||||
"rv64d/I-FNMADD-D-01", "2000",
|
||||
"rv64d/I-FNMSUB-D-01", "2000",
|
||||
"rv64d/I-FSD-01", "2000",
|
||||
"rv64d/I-FSGNJ-D-01", "2000",
|
||||
"rv64d/I-FSGNJN-D-01", "2000",
|
||||
"rv64d/I-FSGNJX-D-01", "2000",
|
||||
"rv64d/I-FSQRTD-01", "2000",
|
||||
"rv64d/I-FSUB-D-01", "2000"
|
||||
"rv64f/I-FCLASS-S-01", "2000"
|
||||
};
|
||||
|
||||
string tests64a[] = '{
|
||||
@ -180,6 +117,7 @@ module testbench();
|
||||
};
|
||||
|
||||
string tests64i[] = '{
|
||||
"rv64i/WALLY-PIPELINE-100K", "f7ff0",
|
||||
"rv64i/I-ADD-01", "3000",
|
||||
"rv64i/I-ADDI-01", "3000",
|
||||
"rv64i/I-ADDIW-01", "3000",
|
||||
@ -324,41 +262,8 @@ module testbench();
|
||||
"rv32i/I-MISALIGN_JMP-01","2000"
|
||||
};
|
||||
|
||||
string tests32f[] = '{
|
||||
"rv32f/I-FADD-S-01", "2000",
|
||||
"rv32f/I-FCLASS-S-01", "2000",
|
||||
"rv32f/I-FCVT-S-L-01", "2000",
|
||||
"rv32f/I-FCVT-S-LU-01", "2000",
|
||||
"rv32f/I-FCVT-S-W-01", "2000",
|
||||
"rv32f/I-FCVT-S-WU-01", "2000",
|
||||
"rv32f/I-FCVT-L-S-01", "2000",
|
||||
"rv32f/I-FCVT-LU-S-01", "2000",
|
||||
"rv32f/I-FCVT-W-S-01", "2000",
|
||||
"rv32f/I-FCVT-WU-S-01", "2000",
|
||||
"rv32f/I-FDIV-S-01", "2000",
|
||||
"rv32f/I-FEQ-S-01", "2000",
|
||||
"rv32f/I-FLE-S-01", "2000",
|
||||
"rv32f/I-FLT-S-01", "2000",
|
||||
"rv32f/I-FMADD-S-01", "2000",
|
||||
"rv32f/I-FMAX-S-01", "2000",
|
||||
"rv32f/I-FMIN-S-01", "2000",
|
||||
"rv32f/I-FMSUB-S-01", "2000",
|
||||
"rv32f/I-FMUL-S-01", "2000",
|
||||
"rv32f/I-FMV-W-X-01", "2000",
|
||||
"rv32f/I-FMV-X-W-01", "2000",
|
||||
"rv32f/I-FNMADD-S-01", "2000",
|
||||
"rv32f/I-FNMSUB-S-01", "2000",
|
||||
"rv32f/I-FSGNJ-S-01", "2000",
|
||||
"rv32f/I-FSGNJN-S-01", "2000",
|
||||
"rv32f/I-FSGNJX-S-01", "2000",
|
||||
"rv32f/I-FSQRT-S-01", "2000",
|
||||
"rv32f/I-FSW-01", "2000",
|
||||
"rv32f/I-FLW-01", "2110",
|
||||
"rv32f/I-FSUB-S-01", "2000"
|
||||
};
|
||||
|
||||
|
||||
string tests32i[] = {
|
||||
"rv32i/WALLY-PIPELINE-100K", "10a800",
|
||||
"rv32i/I-ADD-01", "2000",
|
||||
"rv32i/I-ADDI-01","2000",
|
||||
"rv32i/I-AND-01","2000",
|
||||
@ -374,7 +279,7 @@ string tests32f[] = '{
|
||||
"rv32i/I-EBREAK-01","2000",
|
||||
"rv32i/I-ECALL-01","2000",
|
||||
"rv32i/I-ENDIANESS-01","2010",
|
||||
"rv32i/I-IO-01","2030",
|
||||
"rv32i/I-IO-01","2030rv",
|
||||
"rv32i/I-JAL-01","3000",
|
||||
"rv32i/I-JALR-01","3000",
|
||||
"rv32i/I-LB-01","3020",
|
||||
@ -433,8 +338,7 @@ string tests32f[] = '{
|
||||
"rv32i/WALLY-CSRRC", "4000",
|
||||
"rv32i/WALLY-CSRRWI", "3000",
|
||||
"rv32i/WALLY-CSRRSI", "3000",
|
||||
"rv32i/WALLY-CSRRCI", "3000",
|
||||
"rv32i/WALLY-PIPELINE", "1a800"
|
||||
"rv32i/WALLY-CSRRCI", "3000"
|
||||
};
|
||||
|
||||
string testsBP64[] = '{
|
||||
@ -451,27 +355,26 @@ string tests32f[] = '{
|
||||
"rv64p/WALLY-MTVAL", "6000",
|
||||
"rv64p/WALLY-STVAL", "4000",
|
||||
"rv64p/WALLY-MTVEC", "2000",
|
||||
"rv64p/WALLY-STVEC", "2000",
|
||||
"rv64p/WALLY-MARCHID", "4000",
|
||||
"rv64p/WALLY-MIMPID", "4000",
|
||||
"rv64p/WALLY-MHARTID", "4000",
|
||||
"rv64p/WALLY-MVENDORID", "4000",
|
||||
"rv64p/WALLY-MIE", "3000",
|
||||
"rv64p/WALLY-MEDELEG", "4000"
|
||||
"rv64p/WALLY-MVENDORID", "4000"
|
||||
};
|
||||
|
||||
string tests32p[] = '{
|
||||
"rv32p/WALLY-MCAUSE", "4000",
|
||||
"rv32p/WALLY-SCAUSE", "3000",
|
||||
"rv32p/WALLY-MEPC", "5000",
|
||||
"rv32p/WALLY-SEPC", "4000",
|
||||
"rv32p/WALLY-MTVAL", "5000",
|
||||
"rv32p/WALLY-STVAL", "4000",
|
||||
"rv32p/WALLY-MARCHID", "4000",
|
||||
"rv32p/WALLY-MIMPID", "4000",
|
||||
"rv32p/WALLY-MHARTID", "4000",
|
||||
"rv32p/WALLY-MVENDORID", "4000"
|
||||
//"rv32p/WALLY-MEDELEG", "4000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though.
|
||||
//"rv32p/WALLY-MTVEC", "2000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though.
|
||||
// "rv32p/WALLY-MCAUSE", "4000",
|
||||
// "rv32p/WALLY-SCAUSE", "3000",
|
||||
// "rv32p/WALLY-MEPC", "5000",
|
||||
// "rv32p/WALLY-SEPC", "4000",
|
||||
// "rv32p/WALLY-MTVAL", "5000",
|
||||
// "rv32p/WALLY-STVAL", "4000",
|
||||
// "rv32p/WALLY-MARCHID", "4000",
|
||||
// "rv32p/WALLY-MIMPID", "4000",
|
||||
// "rv32p/WALLY-MHARTID", "4000",
|
||||
// "rv32p/WALLY-MVENDORID", "4000"
|
||||
// "rv32p/WALLY-MTVEC", "2000",
|
||||
// "rv32p/WALLY-STVEC", "2000"
|
||||
};
|
||||
|
||||
string tests64periph[] = '{
|
||||
@ -526,7 +429,7 @@ string tests32f[] = '{
|
||||
if (TESTSPERIPH) begin
|
||||
tests = tests32periph;
|
||||
end else begin
|
||||
tests = {tests32i, tests32p, tests32periph};
|
||||
tests = {tests32i, tests32p};//,tests32periph}; *** broken at the moment
|
||||
if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
|
||||
else tests = {tests, tests32iNOc};
|
||||
if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
|
||||
@ -603,7 +506,7 @@ string tests32f[] = '{
|
||||
$display("Code ended with ecall with gp = 1");
|
||||
#60; // give time for instructions in pipeline to finish
|
||||
// clear signature to prevent contamination from previous tests
|
||||
for(i=0; i<MAXSIGLEN; i=i+1) begin
|
||||
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
||||
sig32[i] = 'bx;
|
||||
end
|
||||
|
||||
@ -611,7 +514,7 @@ string tests32f[] = '{
|
||||
signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"};
|
||||
$readmemh(signame, sig32);
|
||||
i = 0;
|
||||
while (i < MAXSIGLEN) begin
|
||||
while (i < SIGNATURESIZE) begin
|
||||
if (`XLEN == 32) begin
|
||||
signature[i] = sig32[i];
|
||||
i = i+1;
|
||||
@ -716,13 +619,11 @@ module instrNameDecTB(
|
||||
logic [2:0] funct3;
|
||||
logic [6:0] funct7;
|
||||
logic [11:0] imm;
|
||||
logic [4:0] rs2;
|
||||
|
||||
assign op = instr[6:0];
|
||||
assign funct3 = instr[14:12];
|
||||
assign funct7 = instr[31:25];
|
||||
assign imm = instr[31:20];
|
||||
assign rs2 = instr[24:20];
|
||||
|
||||
// it would be nice to add the operands to the name
|
||||
// create another variable called decoded
|
||||
@ -846,67 +747,6 @@ module instrNameDecTB(
|
||||
else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
|
||||
else name = "ILLEGAL";
|
||||
10'b0001111_???: name = "FENCE";
|
||||
10'b1000011_???: name = "FMADD";
|
||||
10'b1000111_???: name = "FMSUB";
|
||||
10'b1001011_???: name = "FNMSUB";
|
||||
10'b1001111_???: name = "FNMADD";
|
||||
10'b1010011_000: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1110000 && rs2 == 5'b00000) name = "FMV.X.W";
|
||||
else if (funct7 == 7'b1111000 && rs2 == 5'b00000) name = "FMV.W.X";
|
||||
else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.W"; // DOUBLE
|
||||
else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.W.X"; // DOUBLE
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
|
||||
else if (funct7[6:2] == 5'b00101) name = "FMIN";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FLE";
|
||||
else name = "ILLEGAL";
|
||||
10'b1010011_001: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
|
||||
else if (funct7[6:2] == 5'b00101) name = "FMAX";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FLT";
|
||||
else if (funct7[6:2] == 5'b11100) name = "FCLASS";
|
||||
else name = "ILLEGAL";
|
||||
10'b0101111_010: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FEQ";
|
||||
else name = "ILLEGAL";
|
||||
10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else name = "ILLEGAL";
|
||||
10'b0000111_010: name = "FLW";
|
||||
10'b0100111_010: name = "FSW";
|
||||
10'b0000111_010: name = "FLD";
|
||||
10'b0100111_010: name = "FSD";
|
||||
default: name = "ILLEGAL";
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
@ -190,7 +190,9 @@ for xlen in xlens:
|
||||
# This is the address we write results to
|
||||
# x6: Starting address we should write expected results to
|
||||
# ...
|
||||
# x1 - x5 can be freely written
|
||||
# x4 & x5 can be freely written
|
||||
# x3 — DO NOT WRITE ANY NON-ZERO VALUE TO THIS — test exits on ecall if x3 = 1 (x3 is gp)
|
||||
# x1 & x2 can be freely written
|
||||
|
||||
|
||||
|
||||
|
||||
@ -51,52 +51,39 @@ def writeVectors(storecmd, returningInstruction):
|
||||
|
||||
|
||||
# Illegal Instruction
|
||||
writeTest(storecmd, f, r, f"""
|
||||
.fill 1, 4, 0
|
||||
""", False, 0)
|
||||
# writeTest(storecmd, f, r, f"""
|
||||
# .fill 1, 4, 0
|
||||
# """, False, 0)
|
||||
|
||||
# Breakpoint
|
||||
if returningInstruction != "ebreak":
|
||||
# # Breakpoint
|
||||
# if returningInstruction != "ebreak":
|
||||
# writeTest(storecmd, f, r, f"""
|
||||
# ebreak
|
||||
# """, False, 0)
|
||||
|
||||
# # Load Address Misaligned
|
||||
# writeTest(storecmd, f, r, f"""
|
||||
# lw x0, 11(x0)
|
||||
# """, False, 0)
|
||||
|
||||
# # Load Access fault: False, 5
|
||||
|
||||
# # Store/AMO address misaligned
|
||||
# writeTest(storecmd, f, r, f"""
|
||||
# sw x0, 11(x0)
|
||||
# """, False, 0)
|
||||
|
||||
# # Environment call from u-mode: only for when only M and U mode enabled?
|
||||
# # writeTest(storecmd, f, r, f"""
|
||||
# # ecall
|
||||
# # """, False, 8, "u")
|
||||
if returningInstruction != "ecall":
|
||||
writeTest(storecmd, f, r, f"""
|
||||
ebreak
|
||||
ecall
|
||||
""", False, 0)
|
||||
|
||||
# Load Address Misaligned
|
||||
writeTest(storecmd, f, r, f"""
|
||||
lw x0, 11(x0)
|
||||
""", False, 0)
|
||||
|
||||
# Load Access fault: False, 5
|
||||
|
||||
# Store/AMO address misaligned
|
||||
writeTest(storecmd, f, r, f"""
|
||||
sw x0, 11(x0)
|
||||
""", False, 0)
|
||||
|
||||
# Environment call from u-mode: only for when only M and U mode enabled?
|
||||
# writeTest(storecmd, f, r, f"""
|
||||
# ecall
|
||||
# """, False, 8, "u")
|
||||
if returningInstruction != "ecall":
|
||||
if fromMode == "u":
|
||||
writeTest(storecmd, f, r, f"""
|
||||
ecall
|
||||
""", False, 0)
|
||||
|
||||
# Environment call from s-mode
|
||||
if fromMode == "s":
|
||||
writeTest(storecmd, f, r, f"""
|
||||
ecall
|
||||
""", False, 0)
|
||||
|
||||
# Environment call from m-mode
|
||||
if fromMode == "m":
|
||||
writeTest(storecmd, f, r, f"""
|
||||
ecall
|
||||
""", False, 0)
|
||||
|
||||
|
||||
if fromMode == "m":
|
||||
if fromMode == "m" and testMode == "m":
|
||||
expectedCode = 7 if fromMode == "m" else 5
|
||||
clintAddr = "0x2004000"
|
||||
|
||||
@ -105,9 +92,9 @@ def writeVectors(storecmd, returningInstruction):
|
||||
csrrs x0, {fromMode}status, x1
|
||||
|
||||
la x18, {clintAddr}
|
||||
lw x11, 0(x18)
|
||||
li x1, 0x3fffffffffffffff
|
||||
{storecmd} x1, 0(x18)
|
||||
# lw x11, 0(x18)
|
||||
# li x1, 0x3fffffffffffffff
|
||||
# {storecmd} x1, 0(x18)
|
||||
|
||||
li x1, 0x80
|
||||
csrrs x0, {fromMode}ie, x1
|
||||
@ -132,7 +119,7 @@ def writeVectors(storecmd, returningInstruction):
|
||||
|
||||
|
||||
def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
|
||||
global testnum, storeAddressOffset
|
||||
global testnum, storeAddressOffset, xlen
|
||||
|
||||
expected = code
|
||||
|
||||
@ -156,19 +143,27 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
|
||||
{test}
|
||||
"""
|
||||
|
||||
lines += f"""
|
||||
|
||||
if not areVectoredTrapsSupported or not vectoredInterrupts:
|
||||
expected = 0
|
||||
|
||||
writeGeneralTest(storecmd, f, r, lines, expected)
|
||||
|
||||
def writeGeneralTest(storecmd, f, r, test, expected):
|
||||
global testnum, storeAddressOffset, xlen
|
||||
|
||||
lines = f"""
|
||||
{test}
|
||||
{storecmd} x25, {testnum * wordsize}(x6)
|
||||
"""
|
||||
|
||||
if not areVectoredTrapsSupported:
|
||||
expected = 0
|
||||
|
||||
f.write(lines)
|
||||
if (xlen == 32):
|
||||
line = formatrefstr.format(expected)+"\n"
|
||||
else:
|
||||
line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
|
||||
r.write(line)
|
||||
|
||||
testnum = testnum+1
|
||||
|
||||
##################################
|
||||
@ -177,7 +172,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
|
||||
|
||||
author = "dottolia@hmc.edu"
|
||||
xlens = [32, 64]
|
||||
testCount = 16;
|
||||
testCount = 4;
|
||||
|
||||
# setup
|
||||
# Change this seed to a different constant value for every test
|
||||
@ -219,6 +214,25 @@ for xlen in xlens:
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# Ensure MODE of *tvec (last 2 bits) is either 00 or 01
|
||||
f.write(f"""
|
||||
csrr x19, {testMode}tvec
|
||||
""")
|
||||
|
||||
for i in range(0, 16):
|
||||
i = i;
|
||||
trySet = i | 0b10;
|
||||
expected = trySet & 0xFFFF_FFFFD;
|
||||
writeGeneralTest(storecmd, f, r, f"""
|
||||
li x1, {trySet}
|
||||
csrw {testMode}tvec, x1
|
||||
csrr x25, {testMode}tvec
|
||||
""", expected)
|
||||
|
||||
f.write(f"""
|
||||
csrw {testMode}tvec, x19
|
||||
""")
|
||||
|
||||
# We need to leave at least one bit in medeleg unset so that we have a way to get
|
||||
# back to machine mode when the tests are complete (otherwise we'll only ever be able
|
||||
# to get up to supervisor mode).
|
||||
@ -233,211 +247,218 @@ for xlen in xlens:
|
||||
# For testgen-TVAL, we don't need to test ebreak, so we can use that as the sole
|
||||
# returning instruction. For others, like testgen-CAUSE, we'll need to put
|
||||
# both ebreak and ecall here.
|
||||
|
||||
|
||||
for returningInstruction in ["ebreak"]:
|
||||
for vectoredInterrupts in [True, False]:
|
||||
|
||||
# All registers used:
|
||||
# x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
|
||||
# ...
|
||||
# x28: address trap handler should jump to for the test
|
||||
# x27: address the test should return to after the test
|
||||
# ...
|
||||
# x25: value to write to memory
|
||||
# ...
|
||||
# x20: intermediate value in trap handler. Don't overwrite this!
|
||||
# x19: mtvec old value
|
||||
# x18: medeleg old value
|
||||
# x17: sedeleg old value (currently unused — user mode traps deprecated)
|
||||
# x16: mideleg old value
|
||||
# ...
|
||||
# x10 - x14 can be freely written
|
||||
# ...
|
||||
# x7: copy of x6. Increment this instead of using an offset on x6.
|
||||
# this allows us to create more than 2048/wordlen tests.
|
||||
# This is the address we write results to
|
||||
# x6: Starting address we should write expected results to
|
||||
# ...
|
||||
# x1 - x5 can be freely written
|
||||
# All registers used:
|
||||
# x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
|
||||
# ...
|
||||
# x28: address trap handler should jump to for the test
|
||||
# x27: address the test should return to after the test
|
||||
# ...
|
||||
# x25: value to write to memory
|
||||
# ...
|
||||
# x20: intermediate value in trap handler. Don't overwrite this!
|
||||
# x19: mtvec old value
|
||||
# x18: medeleg old value
|
||||
# x17: sedeleg old value (currently unused — user mode traps deprecated)
|
||||
# x16: mideleg old value
|
||||
# ...
|
||||
# x10 - x14 can be freely written
|
||||
# ...
|
||||
# x7: copy of x6. Increment this instead of using an offset on x6.
|
||||
# this allows us to create more than 2048/wordlen tests.
|
||||
# This is the address we write results to
|
||||
# x6: Starting address we should write expected results to
|
||||
# ...
|
||||
# x1 - x5 can be freely written
|
||||
|
||||
|
||||
|
||||
# Set up x7 and store old value of mtvec
|
||||
lines = f"""
|
||||
add x7, x6, x0
|
||||
csrr x19, mtvec
|
||||
"""
|
||||
|
||||
# Not used — user mode traps are deprecated
|
||||
if testMode == "u":
|
||||
lines += f"""
|
||||
csrr x17, sedeleg
|
||||
li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
|
||||
csrs sedeleg, x9
|
||||
"""
|
||||
|
||||
# Code that will jump to the test (x28 is set in writeTest above)
|
||||
testJumpCode = f"""
|
||||
auipc x27, 0
|
||||
addi x27, x27, 12
|
||||
jr x28
|
||||
"""
|
||||
|
||||
beforeCode = ""
|
||||
for i in range(0, 16):
|
||||
beforeCode+=f"""
|
||||
nop
|
||||
nop
|
||||
li x25, {i}
|
||||
j _j_m_trap_end_{returningInstruction}
|
||||
# Set up x7 and store old value of mtvec
|
||||
lines = f"""
|
||||
# add x7, x6, x0
|
||||
csrr x19, mtvec
|
||||
"""
|
||||
|
||||
########
|
||||
####### FIXME: wally is causing exception code 1 when you put non 4-bit aligned into mtvec. Bad wally.
|
||||
########
|
||||
|
||||
# Code for handling traps in different modes
|
||||
# Some comments are inside of the below strings (prefixed with a #, as you might expected)
|
||||
lines += f"""
|
||||
# Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
|
||||
li x30, 0
|
||||
|
||||
# Set up
|
||||
la x1, _j_m_trap_{returningInstruction}
|
||||
#addi x1, 1
|
||||
csrw mtvec, x1
|
||||
la x1, _j_s_trap_{returningInstruction}
|
||||
csrw stvec, x1
|
||||
la x1, _j_u_trap_{returningInstruction}
|
||||
# csrw utvec, x1 # user mode traps are not supported
|
||||
|
||||
# Start the tests!
|
||||
j _j_t_begin_{returningInstruction}
|
||||
|
||||
# Machine mode traps
|
||||
_j_m_trap_{returningInstruction}:
|
||||
{beforeCode}
|
||||
|
||||
_j_m_trap_end_{returningInstruction}:
|
||||
{testJumpCode}
|
||||
|
||||
csrrs x20, mepc, x0
|
||||
addi x20, x20, 4
|
||||
csrrw x0, mepc, x20
|
||||
bnez x30, _j_all_end_{returningInstruction}
|
||||
mret
|
||||
|
||||
# Supervisor mode traps
|
||||
_j_s_trap_{returningInstruction}:
|
||||
{testJumpCode if testMode == "s" else "li x25, 0xBAD00001"}
|
||||
|
||||
csrrs x20, sepc, x0
|
||||
addi x20, x20, 4
|
||||
csrrw x0, sepc, x20
|
||||
bnez x30, _j_goto_machine_mode_{returningInstruction}
|
||||
sret
|
||||
|
||||
# Unused: user mode traps are no longer supported
|
||||
_j_u_trap_{returningInstruction}:
|
||||
{testJumpCode if testMode == "u" else "li x25, 0xBAD00000"}
|
||||
|
||||
csrrs x20, uepc, x0
|
||||
addi x20, x20, 4
|
||||
csrrw x0, uepc, x20
|
||||
bnez x30, _j_goto_supervisor_mode_{returningInstruction}
|
||||
uret
|
||||
|
||||
# Currently unused. Just jumps to _j_goto_machine_mode. If you actually
|
||||
# want to implement this, you'll likely need to reset sedeleg here
|
||||
# and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong)
|
||||
_j_goto_supervisor_mode_{returningInstruction}:
|
||||
j _j_goto_machine_mode_{returningInstruction}
|
||||
|
||||
_j_goto_machine_mode_{returningInstruction}:
|
||||
li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction} in the machine trap handler, which we'll get into by invoking...
|
||||
{returningInstruction} # ... this instruction!
|
||||
|
||||
# Run the actual tests!
|
||||
_j_t_begin_{returningInstruction}:
|
||||
"""
|
||||
|
||||
fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
|
||||
|
||||
# We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
|
||||
# back to machine mode at the end! (and we need to be in machine mode to complete the tests)
|
||||
medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
|
||||
|
||||
# Set medeleg and mideleg
|
||||
lines += f"""
|
||||
csrr x18, medeleg
|
||||
li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
|
||||
csrw medeleg, x9
|
||||
|
||||
csrr x16, mideleg
|
||||
li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
|
||||
csrw mideleg, x9
|
||||
"""
|
||||
|
||||
f.write(lines)
|
||||
|
||||
for fromMode in fromModeOptions:
|
||||
lines = ""
|
||||
|
||||
# Code to bring us down to supervisor mode
|
||||
if fromMode == "s" or fromMode == "u":
|
||||
# Not used — user mode traps are deprecated
|
||||
if testMode == "u":
|
||||
lines += f"""
|
||||
li x1, 0b110000000000
|
||||
csrrc x28, mstatus, x1
|
||||
li x1, 0b0100000000000
|
||||
csrrs x28, mstatus, x1
|
||||
csrr x17, sedeleg
|
||||
li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
|
||||
csrs sedeleg, x9
|
||||
"""
|
||||
|
||||
auipc x1, 0
|
||||
addi x1, x1, 16 # x1 is now right after the mret instruction
|
||||
csrw mepc, x1
|
||||
mret
|
||||
# Code that will jump to the test (x28 is set in writeTest above)
|
||||
testJumpCode = f"""
|
||||
auipc x27, 0
|
||||
addi x27, x27, 12
|
||||
jr x28
|
||||
"""
|
||||
|
||||
# We're now in supervisor mode...
|
||||
"""
|
||||
beforeCode = {"m": "", "s": ""}
|
||||
for pm in ["m", "s"]:
|
||||
for i in range(0, 16):
|
||||
beforeCode[pm] = beforeCode[pm] + f"""
|
||||
nop
|
||||
nop
|
||||
li x25, {i}
|
||||
j _j_{pm}_trap_end_{returningInstruction}_{vectoredInterrupts}
|
||||
"""
|
||||
|
||||
# Code to bring us down to user mode
|
||||
if fromMode == "u":
|
||||
lines += f"""
|
||||
# Code for handling traps in different modes
|
||||
# Some comments are inside of the below strings (prefixed with a #, as you might expected)
|
||||
enableVectored = "addi x1, x1, 1" if vectoredInterrupts else ""
|
||||
|
||||
li x1, 0b110000000000
|
||||
csrrc x28, sstatus, x1
|
||||
lines += f"""
|
||||
# Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
|
||||
li x30, 0
|
||||
|
||||
auipc x1, 0
|
||||
addi x1, x1, 16 # x1 is now right after the sret instruction
|
||||
csrw sepc, x1
|
||||
# Set up
|
||||
la x1, _j_m_trap_{returningInstruction}_{vectoredInterrupts}
|
||||
{enableVectored} # enable/don't enable vectored interrupts
|
||||
csrw mtvec, x1
|
||||
la x1, _j_s_trap_{returningInstruction}_{vectoredInterrupts}
|
||||
{enableVectored} # enable/don't enable vectored interrupts
|
||||
csrw stvec, x1
|
||||
la x1, _j_u_trap_{returningInstruction}_{vectoredInterrupts}
|
||||
{enableVectored} # enable/don't enable vectored interrupts
|
||||
# csrw utvec, x1 # user mode traps are not supported
|
||||
|
||||
# Start the tests!
|
||||
j _j_t_begin_{returningInstruction}_{vectoredInterrupts}
|
||||
|
||||
# Machine mode traps
|
||||
_j_m_trap_{returningInstruction}_{vectoredInterrupts}:
|
||||
{beforeCode['m']}
|
||||
|
||||
_j_m_trap_end_{returningInstruction}_{vectoredInterrupts}:
|
||||
{testJumpCode}
|
||||
|
||||
csrrs x20, mepc, x0
|
||||
addi x20, x20, 4
|
||||
csrrw x0, mepc, x20
|
||||
bnez x30, _j_all_end_{returningInstruction}_{vectoredInterrupts}
|
||||
mret
|
||||
|
||||
# Supervisor mode traps
|
||||
_j_s_trap_{returningInstruction}_{vectoredInterrupts}:
|
||||
{beforeCode['s']}
|
||||
|
||||
_j_s_trap_end_{returningInstruction}_{vectoredInterrupts}:
|
||||
{testJumpCode}
|
||||
|
||||
csrrs x20, sepc, x0
|
||||
addi x20, x20, 4
|
||||
csrrw x0, sepc, x20
|
||||
bnez x30, _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}
|
||||
sret
|
||||
|
||||
# We're now in user mode...
|
||||
"""
|
||||
# Unused: user mode traps are no longer supported
|
||||
_j_u_trap_{returningInstruction}_{vectoredInterrupts}:
|
||||
{testJumpCode if testMode == "u" else "li x25, 0xBAD00000"}
|
||||
|
||||
csrrs x20, uepc, x0
|
||||
addi x20, x20, 4
|
||||
csrrw x0, uepc, x20
|
||||
bnez x30, _j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts}
|
||||
uret
|
||||
|
||||
# Currently unused. Just jumps to _j_goto_machine_mode. If you actually
|
||||
# want to implement this, you'll likely need to reset sedeleg here
|
||||
# and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong)
|
||||
_j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts}:
|
||||
j _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}
|
||||
|
||||
_j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}:
|
||||
li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction}_{vectoredInterrupts} in the machine trap handler, which we'll get into by invoking...
|
||||
{returningInstruction} # ... this instruction!
|
||||
|
||||
# Run the actual tests!
|
||||
_j_t_begin_{returningInstruction}_{vectoredInterrupts}:
|
||||
"""
|
||||
|
||||
fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
|
||||
|
||||
# We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
|
||||
# back to machine mode at the end! (and we need to be in machine mode to complete the tests)
|
||||
medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
|
||||
|
||||
# Set medeleg and mideleg
|
||||
lines += f"""
|
||||
csrr x18, medeleg
|
||||
li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
|
||||
csrw medeleg, x9
|
||||
|
||||
csrr x16, mideleg
|
||||
li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
|
||||
csrw mideleg, x9
|
||||
"""
|
||||
|
||||
f.write(lines)
|
||||
for i in range(0,testCount):
|
||||
writeVectors(storecmd, returningInstruction)
|
||||
|
||||
for fromMode in fromModeOptions:
|
||||
lines = ""
|
||||
|
||||
# Code to bring us down to supervisor mode
|
||||
if fromMode == "s" or fromMode == "u":
|
||||
lines += f"""
|
||||
li x1, 0b110000000000
|
||||
csrrc x28, mstatus, x1
|
||||
li x1, 0b0100000000000
|
||||
csrrs x28, mstatus, x1
|
||||
|
||||
auipc x1, 0
|
||||
addi x1, x1, 16 # x1 is now right after the mret instruction
|
||||
csrw mepc, x1
|
||||
mret
|
||||
|
||||
# We're now in supervisor mode...
|
||||
"""
|
||||
|
||||
# Code to bring us down to user mode
|
||||
if fromMode == "u":
|
||||
lines += f"""
|
||||
|
||||
li x1, 0b110000000000
|
||||
csrrc x28, sstatus, x1
|
||||
|
||||
auipc x1, 0
|
||||
addi x1, x1, 16 # x1 is now right after the sret instruction
|
||||
csrw sepc, x1
|
||||
sret
|
||||
|
||||
# We're now in user mode...
|
||||
"""
|
||||
|
||||
f.write(lines)
|
||||
for i in range(0,testCount):
|
||||
writeVectors(storecmd, returningInstruction)
|
||||
|
||||
|
||||
# Very end of test. Bring us back up to machine mode
|
||||
# We set x30 to 1, which will cause us to branch to _j_all_end in the
|
||||
# machine mode trap handler, before executing the mret instruction. This will
|
||||
# make us stay in machine mode.
|
||||
#
|
||||
# If we're currently in user mode, this will first bump us up to the supervisor mode
|
||||
# trap handler, which will call returningInstruction again before it's sret instruction,
|
||||
# bumping us up to machine mode
|
||||
#
|
||||
# Get into the trap handler by running returningInstruction (either an ecall or ebreak)
|
||||
f.write(f"""
|
||||
li x30, 1
|
||||
li gp, 0
|
||||
{returningInstruction}
|
||||
_j_all_end_{returningInstruction}:
|
||||
# Very end of test. Bring us back up to machine mode
|
||||
# We set x30 to 1, which will cause us to branch to _j_all_end in the
|
||||
# machine mode trap handler, before executing the mret instruction. This will
|
||||
# make us stay in machine mode.
|
||||
#
|
||||
# If we're currently in user mode, this will first bump us up to the supervisor mode
|
||||
# trap handler, which will call returningInstruction again before it's sret instruction,
|
||||
# bumping us up to machine mode
|
||||
#
|
||||
# Get into the trap handler by running returningInstruction (either an ecall or ebreak)
|
||||
f.write(f"""
|
||||
li x30, 1
|
||||
li gp, 0
|
||||
{returningInstruction}
|
||||
_j_all_end_{returningInstruction}_{vectoredInterrupts}:
|
||||
|
||||
# Reset trap handling csrs to old values
|
||||
csrw mtvec, x19
|
||||
csrw medeleg, x18
|
||||
csrw mideleg, x16
|
||||
""")
|
||||
# Reset trap handling csrs to old values
|
||||
csrw mtvec, x19
|
||||
csrw medeleg, x18
|
||||
csrw mideleg, x16
|
||||
""")
|
||||
|
||||
# print footer
|
||||
h = open("../testgen_footer.S", "r")
|
||||
@ -450,8 +471,3 @@ for xlen in xlens:
|
||||
f.write(lines)
|
||||
f.close()
|
||||
r.close()
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -513,7 +513,7 @@ class RegFile():
|
||||
for immutableRegKey, immutableRegVal in immutableRegsDict.items():
|
||||
self.regs[immutableRegKey].setValue(newValue = immutableRegVal, signed = 1)
|
||||
self.immutableRegsList.append(immutableRegKey)
|
||||
|
||||
|
||||
def getRandReg(self):
|
||||
reg = randint(1, len(self.regs)-1)
|
||||
while(reg in self.immutableRegsList):
|
||||
@ -584,10 +584,7 @@ class Memory():
|
||||
if addr not in self.memDict.keys():
|
||||
errStr = 'Tried to read from uninitialized address: {}'.format(addr)
|
||||
raise ReadFromUninitializedMemoryException(errStr)
|
||||
# # get a random number of grandularity
|
||||
# self.memDict[addr] = self.genRandMemoryValue()
|
||||
# get value from memory
|
||||
# print(self.memDict.items())
|
||||
|
||||
val = self.memDict[addr]
|
||||
if granularity == GRANULARITY.WORD:
|
||||
val = val
|
||||
@ -638,6 +635,10 @@ class TestGen():
|
||||
|
||||
self.imperasPath = imperasPath + instrSet.lower() + '/'
|
||||
self.exportTestName = 'PIPELINE'
|
||||
if (self.numInstr == 100000):
|
||||
self.exportTestName += "-100K"
|
||||
elif (self.numInstr == 1000000):
|
||||
self.exportTestName += "-1M"
|
||||
self.basename = 'WALLY-'+ self.exportTestName
|
||||
self.fname = self.imperasPath + "src/" + self.basename + ".S"
|
||||
self.refname = self.imperasPath + "references/" + self.basename + ".reference_output"
|
||||
@ -647,9 +648,9 @@ class TestGen():
|
||||
reg6 = self.model.regFile.regs[6]
|
||||
out = [Instr.issue(model = self.model, instrName = "sw", rs2 = reg, imm = imm, rs1 = reg6)]
|
||||
self.model.resultImmediateCounter += 4
|
||||
if (self.model.resultImmediateCounter == 2044):
|
||||
if (self.model.resultImmediateCounter == 2040):
|
||||
# Reset
|
||||
imm2 = Immediate.setImm12(xlen = self.xlen, value = 2044)
|
||||
imm2 = Immediate.setImm12(xlen = self.xlen, value = 2040)
|
||||
reg6.setImmutable(False)
|
||||
wreset = Instr.issue(model = self.model, instrName = "addi", rd = reg6, imm = imm2, rs1 = reg6)
|
||||
reg6.setImmutable(True)
|
||||
@ -928,14 +929,20 @@ class TestGen():
|
||||
instructions = []
|
||||
|
||||
rd = self.model.regFile.getRandReg()
|
||||
|
||||
memVal = self.model.memoryImmediateCounter
|
||||
reg1 = self.model.regFile.regs[7]
|
||||
|
||||
|
||||
memVal = self.model.memoryImmediateCounter
|
||||
self.model.memoryImmediateCounter += 4
|
||||
if (self.model.memoryImmediateCounter == 2044):
|
||||
if instr == "ld":
|
||||
if ((memVal + reg1.getValueUnsigned()) % 8) != 0:
|
||||
memVal -= 4
|
||||
self.model.memoryImmediateCounter -= 4 # we haven't read from a new location
|
||||
|
||||
|
||||
|
||||
if (self.model.memoryImmediateCounter == 2040):
|
||||
self.model.memoryImmediateCounter = 0
|
||||
immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2044)
|
||||
immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2040)
|
||||
instructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = reg1, rs1 = reg1, imm = immMem))
|
||||
|
||||
|
||||
@ -1062,19 +1069,19 @@ class TestGen():
|
||||
|
||||
rs1 = self.model.regFile.getRandReg()
|
||||
while (rs1 == reg_pc):
|
||||
rs1 = self.model.regFile.getRandReg()
|
||||
|
||||
rs1 = self.model.regFile.getRandReg()
|
||||
|
||||
# TODO fix the value of rs1 - should be pc location of "1f"
|
||||
rs1.setValue(newValue = 0)
|
||||
|
||||
imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
|
||||
|
||||
jumpDestVal = self.model.pc.value + numInstr * 4 + 8
|
||||
generatedInstructions.append('li {}, MASK_XLEN({})'.format(rs1.regName ,jumpDestVal))
|
||||
self.model.pc += 8
|
||||
|
||||
instructions.append('la {}, {}'.format(rs1.regName , "1f"))
|
||||
self.model.pc += 8
|
||||
|
||||
newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm, dir = "f")
|
||||
newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm)
|
||||
instructions.append(newInstr)
|
||||
|
||||
|
||||
# add random alu instructions after jumping before jump point
|
||||
reg_check = self.model.regFile.getRandReg()
|
||||
for i in range(0, numInstr):
|
||||
@ -1086,6 +1093,9 @@ class TestGen():
|
||||
r2 = self.model.regFile.getRandReg()
|
||||
instructions.append(Instr.issue(model = self.model, instrName = "and", rd = rd, rs1 = r1, rs2 = r2))
|
||||
|
||||
instructions.append("1:")
|
||||
self.model.pc += 4
|
||||
|
||||
#make sure jump was taken
|
||||
check_instr = self.genTestInstr(reg_check)
|
||||
for check in check_instr:
|
||||
@ -1106,6 +1116,8 @@ class TestGen():
|
||||
instructions.append(newInstr)
|
||||
# instructions.append("jal x" + reg1 + ", 1f")
|
||||
|
||||
instructions.append("2:")
|
||||
self.model.pc += 4
|
||||
|
||||
newInstr = Instr.issue(model = self.model, instrName='jal', rd = reg2, label = label3, dir = "f")
|
||||
instructions.append(newInstr)
|
||||
@ -1121,40 +1133,47 @@ class TestGen():
|
||||
|
||||
imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
|
||||
|
||||
|
||||
|
||||
generatedInstructions.append('li {}, MASK_XLEN({})'.format(rs1.regName ,jumpDestVal))
|
||||
instructions.append('la {}, {}'.format(rs1.regName ,"2b"))
|
||||
self.model.pc += 8
|
||||
|
||||
|
||||
rs1 = self.model.regFile.regs[0]
|
||||
imm = Immediate.setImm12(xlen = self.model.xlen, value = jumpDestVal)
|
||||
rs1.setValue(newValue = 0) #TODO: this value is wrong, should be address of label
|
||||
imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
|
||||
|
||||
|
||||
numInstr = np.random.randint(0,6)
|
||||
for i in range(0, numInstr):
|
||||
rd = self.model.regFile.getRandReg()
|
||||
while(rd == rs1) or (rd == reg_pc):
|
||||
rd = self.model.regFile.getRandReg()
|
||||
r1 = self.model.regFile.getRandReg()
|
||||
r2 = self.model.regFile.getRandReg()
|
||||
instructions.append(Instr.issue(model = self.model, instrName = 'and', rd = rd, rs1 = r1, rs2 = r2))
|
||||
|
||||
#test case here
|
||||
newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg2, rs1 = rs1, imm = imm, dir = "b")
|
||||
newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm)
|
||||
instructions.append(newInstr)
|
||||
# instructions.append("jal x" + reg2 + ", 2b")
|
||||
instructions.append("3:")
|
||||
self.model.pc += 4
|
||||
|
||||
check_instr = self.genTestInstr(reg1)
|
||||
for check in check_instr:
|
||||
instructions.append(check)
|
||||
|
||||
check_instr = self.genTestInstr(reg_pc)
|
||||
for check in check_instr:
|
||||
instructions.append(check)
|
||||
|
||||
# jump to 1
|
||||
# #2
|
||||
# jump to 3
|
||||
# #1
|
||||
# junk instructions
|
||||
# ...
|
||||
# ...
|
||||
# test instruction
|
||||
# test instruction to 2
|
||||
# #3
|
||||
# check answer from 1
|
||||
return instructions
|
||||
@ -1226,17 +1245,23 @@ class TestGen():
|
||||
|
||||
elif randInstr in InstrTypes['I']:
|
||||
if randInstr == "jalr":
|
||||
# newInstr = self.jumpRInstruction(instr = randInstr)
|
||||
# for i in newInstr:
|
||||
# generatedInstructions.append(i)
|
||||
continue
|
||||
newInstr = self.jumpRInstruction(instr = randInstr)
|
||||
for i in newInstr:
|
||||
generatedInstructions.append(i)
|
||||
# memory instruction
|
||||
elif randInstr[0] == 'l':
|
||||
rd = self.model.regFile.getRandReg()
|
||||
rs1 = self.model.regFile.regs[7]
|
||||
|
||||
memLocation = list(self.model.memory.memDict.keys())[randint(0, len(self.model.memory.memDict.keys()) -1)]
|
||||
|
||||
memLocation = list(self.model.memory.memDict.keys())[randint(0, len(self.model.memory.memDict.keys()) -1)]
|
||||
if randInstr == "ld":
|
||||
if ((memLocation + rs1.getValueUnsigned()) % 8) != 0:
|
||||
if (memLocation != 0):
|
||||
memLocation -=4
|
||||
else:
|
||||
memLocation = 4
|
||||
|
||||
rd = self.model.regFile.getRandReg()
|
||||
|
||||
imm12 = Immediate.setImm12(xlen = self.model.xlen, value = memLocation)
|
||||
instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, rs1 = rs1, imm = imm12)
|
||||
generatedInstructions.append(instr)
|
||||
@ -1257,13 +1282,20 @@ class TestGen():
|
||||
generatedInstructions.append(testInstr)
|
||||
|
||||
elif randInstr in InstrTypes['S']:
|
||||
rs2 = self.model.regFile.getRandReg()
|
||||
rs1 = self.model.regFile.regs[7]
|
||||
|
||||
|
||||
immValue = self.model.memoryImmediateCounter
|
||||
self.model.memoryImmediateCounter += 4
|
||||
immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2044)
|
||||
if (self.model.memoryImmediateCounter == 2044):
|
||||
if randInstr == 'Sd':
|
||||
if ((immValue + rs1.getValueUnsigned()) % 8) != 0:
|
||||
immValue -= 4
|
||||
self.model.memoryImmediateCounter -= 4 #haven't put a value in a new mem locatoin
|
||||
|
||||
rs2 = self.model.regFile.getRandReg()
|
||||
|
||||
|
||||
immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2040)
|
||||
if (self.model.memoryImmediateCounter == 2040):
|
||||
self.model.memoryImmediateCounter = 0
|
||||
generatedInstructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = rs1, rs1 = rs1, imm = immMem))
|
||||
|
||||
@ -1331,7 +1363,10 @@ class TestGen():
|
||||
hexVal = int(self.model.memory.memDict[memLoc],2)
|
||||
hexDigitSize = self.model.xlen / 4
|
||||
formattedStr = '0x{0:0{1}x}'.format(hexVal, hexDigitSize)
|
||||
asmFile.write('\t.word {}\n'.format(formattedStr))
|
||||
if self.model.xlen == 64:
|
||||
asmFile.write('\t.dword {}\n'.format(formattedStr))
|
||||
else:
|
||||
asmFile.write('\t.word {}\n'.format(formattedStr))
|
||||
lineNum += 1
|
||||
|
||||
asmFile.write("\n")
|
||||
@ -1685,6 +1720,148 @@ class Instr():
|
||||
return 'jal {}, {}{}'.format(rd.getRegName(), label.name, dir)
|
||||
|
||||
|
||||
|
||||
|
||||
###################################################################################################
|
||||
# RV 64I
|
||||
###################################################################################################
|
||||
#TODO These may not keep the internal model consistent. You have been warned...sorry lol
|
||||
|
||||
@classmethod
|
||||
def Instr_ld(self, model, rd = None, rs1 = None, imm = None):
|
||||
addr = imm.getDecValue()
|
||||
rd.setBits(newBits = signExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.WORD), \
|
||||
resultNumBits = model.xlen))
|
||||
model.pc += 4
|
||||
return 'ld {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_lwu(self, model, rd = None, rs1 = None, imm = None):
|
||||
addr = imm.getDecValue()
|
||||
rd.setBits(newBits = zeroExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.BYTE), \
|
||||
resultNumBits = model.xlen))
|
||||
model.pc += 4
|
||||
return 'lwu {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_addiw(self, model, rd = None, rs1 = None, imm = None):
|
||||
newValue = rs1.getDecValue() + imm.getDecValue()
|
||||
newValueBin = 0
|
||||
if newValue > 0:
|
||||
newValueBin = bin(newValue)[2:]
|
||||
elif newValue == 0:
|
||||
newValueBin = "0" * model.xlen
|
||||
else:
|
||||
newValueBin = bin(newValue)[3:]
|
||||
newValueBinTrunk = newValueBin[-model.xlen:]
|
||||
rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
|
||||
model.pc += 4
|
||||
return 'addiw {}, {}, MASK_XLEN({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue())
|
||||
|
||||
@classmethod
|
||||
def Instr_slliw(self, model, rd = None, rs1 = None, imm = None):
|
||||
bits = rs1.bits
|
||||
immBits = imm.bits[-5:]
|
||||
immShift = int(immBits, 2)
|
||||
shifted = bits[-(len(bits) - immShift):]
|
||||
shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted)))
|
||||
rd.setValue(newValue = shiftedExt, signed = 1)
|
||||
model.pc += 4
|
||||
return 'slliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
|
||||
|
||||
@classmethod
|
||||
def Instr_srliw(self, model, rd = None, rs1 = None, imm = None):
|
||||
bits = rs1.bits
|
||||
immBits = imm.bits[-5:]
|
||||
immShift = int(immBits, 2)
|
||||
shifted = bits[0:len(bits) - immShift]
|
||||
extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen)
|
||||
rd.setBits(newBits = extShifted, signed = 1)
|
||||
model.pc += 4
|
||||
return 'srliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
|
||||
|
||||
@classmethod
|
||||
def Instr_sraiw(self, model, rd = None, rs1 = None, imm = None):
|
||||
bits = rs1.bits
|
||||
immBits = imm.bits[-5:]
|
||||
immShift = int(immBits, 2)
|
||||
shifted = bits[0:len(bits) - immShift]
|
||||
extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen)
|
||||
rd.setBits(newBits = extShifted, signed = 1)
|
||||
model.pc += 4
|
||||
return 'sraiw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
|
||||
|
||||
@classmethod
|
||||
def Instr_Sd(self, model, rs1 = None, rs2 = None, imm = None):
|
||||
addr = imm.getDecValue()
|
||||
model.memory.updateMemory(addr = addr, value = rs2.bits, granularity = GRANULARITY.WORD)
|
||||
model.pc += 4
|
||||
return 'Sd {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_addw(self, model, rd = None, rs1 = None, rs2 = None):
|
||||
newValue = rs1.getDecValue() + rs2.getDecValue()
|
||||
newValueBin = 0
|
||||
if newValue > 0:
|
||||
newValueBin = bin(newValue)[2:]
|
||||
elif newValue == 0:
|
||||
newValueBin = "0" * model.xlen
|
||||
else:
|
||||
newValueBin = bin(newValue)[3:]
|
||||
newValueBinTrunk = newValueBin[-model.xlen:]
|
||||
rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
|
||||
model.pc += 4
|
||||
return 'addw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_subw(self, model, rd = None, rs1 = None, rs2 = None):
|
||||
newValue = rs1.getDecValue() - rs2.getDecValue()
|
||||
newValueBin = 0
|
||||
if newValue > 0:
|
||||
newValueBin = bin(newValue)[2:]
|
||||
elif newValue == 0:
|
||||
newValueBin = "0" * model.xlen
|
||||
else:
|
||||
newValueBin = bin(newValue)[3:]
|
||||
newValueBinTrunk = newValueBin[-model.xlen:]
|
||||
rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
|
||||
model.pc += 4
|
||||
return 'subw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_sllw(self, model, rd = None, rs1 = None, rs2 = None):
|
||||
bits = rs1.bits
|
||||
rs2Bin = rs2.bits[-5:]
|
||||
rs2Shift = int(rs2Bin,2)
|
||||
shifted = bits[-(len(bits) - rs2Shift):]
|
||||
shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted)))
|
||||
rd.setValue(newValue = shiftedExt, signed = 1)
|
||||
model.pc += 4
|
||||
return 'sllw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_srlw(self, model, rd = None, rs1 = None, rs2 = None):
|
||||
bits = rs1.bits
|
||||
rs2Bin = rs2.bits[-5:]
|
||||
rs2Shift = int(rs2Bin,2)
|
||||
shifted = bits[0:len(bits) - rs2Shift]
|
||||
extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen)
|
||||
rd.setBits(newBits = extShifted, signed = 1)
|
||||
model.pc += 4
|
||||
return 'srlw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
|
||||
|
||||
@classmethod
|
||||
def Instr_sraw(self, model, rd = None, rs1 = None, rs2 = None):
|
||||
bits = rs1.bits
|
||||
rs2Bin = rs2.bits[-5:]
|
||||
rs2Shift = int(rs2Bin,2)
|
||||
shifted = bits[0:len(bits) - rs2Shift]
|
||||
extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen)
|
||||
rd.setBits(newBits = extShifted, signed = 1)
|
||||
model.pc += 4
|
||||
return 'sraw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
|
||||
|
||||
|
||||
###################################################################################################
|
||||
# Global Constants
|
||||
###################################################################################################
|
||||
@ -1693,7 +1870,7 @@ GRANULARITY = Enum('granularity', ['WORD', 'HALFWORD', 'BYTE'])
|
||||
INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \
|
||||
'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \
|
||||
'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \
|
||||
'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal'], \
|
||||
'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal', 'jalr'], \
|
||||
'RV64I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \
|
||||
'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \
|
||||
'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \
|
||||
@ -1703,9 +1880,11 @@ INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti',
|
||||
}
|
||||
|
||||
|
||||
InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and'], \
|
||||
'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr'], \
|
||||
'S' : ['sw', 'sh', 'sb'], \
|
||||
InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', \
|
||||
'addw', 'subw', 'sllw', 'srlw', 'sraw'], \
|
||||
'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr', \
|
||||
'ld', 'lwu', 'addiw', 'slliw', 'srliw', 'sraiw'], \
|
||||
'S' : ['sw', 'sh', 'sb', 'Sd'], \
|
||||
'B' : ['beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu'], \
|
||||
'U' : ['lui', 'auipc'], \
|
||||
'J' : ['jal'], \
|
||||
@ -1714,27 +1893,25 @@ InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra',
|
||||
# Main Body
|
||||
###################################################################################################
|
||||
|
||||
XLEN = ['32']
|
||||
XLEN = ['32', '64']
|
||||
INSTRUCTION_TYPE = ['I']
|
||||
NUMINSTR = 70000
|
||||
NUMINSTR = [100000, 1000000]
|
||||
IMPERASPATH = "../../imperas-riscv-tests/riscv-test-suite/"
|
||||
|
||||
seed(42)
|
||||
np.random.seed(42)
|
||||
for xlen in XLEN:
|
||||
memInit = {}
|
||||
for i in range(0, 400, 4):
|
||||
val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1)
|
||||
memInit[i] = val
|
||||
for instrType in INSTRUCTION_TYPE:
|
||||
instrSet = 'RV' + xlen + instrType
|
||||
|
||||
print('Generating Assembly for {}'.format(instrSet))
|
||||
|
||||
dut = TestGen(numInstr=NUMINSTR, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH)
|
||||
# regFile =
|
||||
dut.model.memory.populateMemory(memDict = memInit)
|
||||
dut.exportASM(instrSet = instrSet, instrTypes = instrType)
|
||||
|
||||
|
||||
for num_instructions in NUMINSTR:
|
||||
for xlen in XLEN:
|
||||
memInit = {}
|
||||
for i in range(0, 400, 4):
|
||||
val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1)
|
||||
memInit[i] = val
|
||||
for instrType in INSTRUCTION_TYPE:
|
||||
instrSet = 'RV' + xlen + instrType
|
||||
|
||||
print('Generating {} Assembly Instructions for {}'.format(num_instructions, instrSet))
|
||||
|
||||
dut = TestGen(numInstr=num_instructions, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH)
|
||||
# regFile =
|
||||
dut.model.memory.populateMemory(memDict = memInit)
|
||||
dut.exportASM(instrSet = instrSet, instrTypes = instrType)
|
||||
Loading…
Reference in New Issue
Block a user