Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-30 16:34:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

Remove busy-mmu and fix missing signal

Browse Source
This commit is contained in:
Thomas Fleming 2021-05-14 07:14:20 -04:00
parent 980c00fa64
commit 1fc607b399
2 changed files with 1 additions and 5204 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5203
wally-pipelined/regression/busy-mmu.do
View File

File diff suppressed because it is too large Load Diff

2
wally-pipelined/src/wally/wallypipelinedhart.sv
View File

@ -120,7 +120,7 @@ module wallypipelinedhart (
logic ICacheStallF;
logic [`XLEN-1:0] MMUPAdr, MMUReadPTE;
logic MMUStall;
logic MMUTranslate, MMUTranslationComplete, MMUReady;
logic MMUTranslate, MMUReady;
// bus interface to dmem
logic MemReadM, MemWriteM;