Thomas Fleming 5946b860ca Comment out fpu from hart until module exists		2021-04-03 22:34:11 -04:00
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cache	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
dmem	Complete basic page table walker	2021-03-30 22:19:27 -04:00
ebu	Fix extraneous page fault stall	2021-04-03 21:28:24 -04:00
fpu	Integrated FPU	2021-04-03 20:52:26 +00:00
generic	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
hazard	Partial fix to the integer divide stall issue.	2021-04-02 15:32:15 -05:00
ieu	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
ifu	Implement sfence.vma and fix tlb writing	2021-04-01 15:55:05 -04:00
mmu	Fix extraneous page fault stall	2021-04-03 21:28:24 -04:00
muldiv	Partial fix to the integer divide stall issue.	2021-04-02 15:32:15 -05:00
privileged	Implement sfence.vma and fix tlb writing	2021-04-01 15:55:05 -04:00
tlb_toy	Install tlb into ifu	2021-03-04 03:11:34 -05:00
uncore	added 1 tick delay to dtim flops	2021-03-25 02:23:30 -04:00
wally	Comment out fpu from hart until module exists	2021-04-03 22:34:11 -04:00