The clock gater was not implemented correctly. Now it is level sensitive to a low clock.

This commit is contained in:
Ross Thompson 2021-06-01 15:05:22 -05:00
parent 8e330367ac
commit 7afbd8d877

View File

@ -38,7 +38,7 @@ module clockgater
logic enable_q;
always @(E or SE) begin
always @(~CLK) begin
enable_q <= E | SE;
end
assign ECLK = enable_q & CLK;