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573 Commits

Author SHA1 Message Date
Ross Thompson
1586f893b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 16:30:55 -05:00
Ross Thompson
7e05935348 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 15:50:04 -05:00
Ross Thompson
e81f317764 Notes on what to change in ram.sv. 2022-03-31 15:48:15 -05:00
bbracker
d32e1147bf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 13:46:32 -07:00
bbracker
34c94f150e simplify plic logic 2022-03-31 13:46:24 -07:00
David Harris
2ed1c9f14f Added SystemVerilog flag to fma.do so that fma16 compiles properly 2022-03-31 17:00:38 +00:00
Ross Thompson
fb0eec0f76 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:39:41 -05:00
Ross Thompson
0942429b7f Forced to go back to hard coded preload. 2022-03-31 11:39:37 -05:00
Ross Thompson
a6d090a7c0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:38:55 -05:00
Ross Thompson
dc48d84dd6 Modified clint to support all byte write sizes. 2022-03-31 11:31:52 -05:00
David Harris
93d6b2fb62 Added synthesis script for fma16 2022-03-31 00:51:33 +00:00
David Harris
f917ed7ed0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 23:06:36 +00:00
bbracker
54b9745a75 big interrupts refactor 2022-03-30 13:22:41 -07:00
Ross Thompson
b2a77da96b Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
David Harris
44f94173bf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:26:27 +00:00
David Harris
1f10a96aa2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:13:42 +00:00
Ross Thompson
3ac736e2d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-30 11:09:44 -05:00
Ross Thompson
370a075fa1 Partial cleanup of memories. 2022-03-30 11:09:21 -05:00
Ross Thompson
1993069986 Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload. 2022-03-30 11:04:15 -05:00
Ross Thompson
fc2b4453ec rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00
Ross Thompson
de2672231d Partial fix to allow byte write enables with fpga and still get a preload to work. 2022-03-29 19:12:29 -05:00
Kip Macsai-Goren
b252122d62 fixed arch bge test signature output location after update 2022-03-29 20:45:18 +00:00
David Harris
057ee56d7e Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv 2022-03-29 19:16:41 +00:00
David Harris
049c55769a fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Kip Macsai-Goren
ad106e7130 made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes 2022-03-29 02:26:42 +00:00
Kip Macsai-Goren
c32f5e9cee fixed signature location of the new periph with no compressed instructions 2022-03-29 02:15:17 +00:00
bbracker
46ffa4b079 fix typo that Madeleine found 2022-03-28 15:39:29 -07:00
Kip Macsai-Goren
dc9635b757 fixed double multiplication on vectored interrupts 2022-03-28 19:12:31 +00:00
Kip Macsai-Goren
2e68ab7bb4 added test config that doesn't use compressed instructions for privileged tests 2022-03-28 19:12:31 +00:00
Skylar Litz
29d1f64588 add AtemptedInstructionCount signal 2022-03-26 21:28:57 +00:00
Skylar Litz
bb8587e06f update to match new filesystem organization 2022-03-26 21:28:32 +00:00
Kip Macsai-Goren
8cde06b886 added basic trap tests that do not pass regression yet. updated signature adresses 2022-03-25 22:57:41 +00:00
Ross Thompson
7099259ff7 I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit. 2022-03-25 13:10:31 -05:00
Ross Thompson
7a824eaae1 Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB. 2022-03-24 23:47:28 -05:00
bbracker
b08066381a fix multiple-context PLIC checkpoint generation 2022-03-25 01:02:22 +00:00
bbracker
150a7b234b tabs vs spaces disagreement 2022-03-24 17:11:41 -07:00
bbracker
9f60256f22 1st attempt at multiple channel PLIC 2022-03-24 17:08:10 -07:00
Ross Thompson
58668812c1 Moved WriteDataM register into LSU. 2022-03-23 14:17:59 -05:00
Ross Thompson
07b7dbc922 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-23 14:10:38 -05:00
Katherine Parry
abdbc31d14 fixed typo in unpack.sv 2022-03-23 18:26:59 +00:00
Ross Thompson
f1787670d4 Cleanup in testbench-linux.sv. 2022-03-22 22:34:38 -05:00
Ross Thompson
6c9750c725 reverted temporary change to configs. 2022-03-22 22:31:34 -05:00
Katherine Parry
ead88fba55 fixed lint error in fpudivsqrtrecur.sv 2022-03-23 03:24:41 +00:00
Ross Thompson
6ab14d7302 Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing. 2022-03-22 22:04:06 -05:00
Ross Thompson
600a97982f Reverted change to configuration which caused issue with lint. 2022-03-22 21:44:08 -05:00
Ross Thompson
c5be2cb1d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-22 21:28:50 -05:00
Ross Thompson
7fc128ba7c added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP. 2022-03-22 21:28:34 -05:00
Katherine Parry
c3c764a171 unpack.sv cleanup 2022-03-23 01:53:37 +00:00
Ross Thompson
80d376877a Added spoof of uart addresses +0x2 and +0x6. 2022-03-22 16:52:27 -05:00
Ross Thompson
cec7625d91 Added comment about needed fix to misaligned fault. 2022-03-22 16:52:07 -05:00
Katherine Parry
2042374102 FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
Ross Thompson
d347de8c49 dtim writes are supressed on non cacheable operation. 2022-03-12 00:46:11 -06:00
Ross Thompson
d8947fa616 cleanup of ram.sv 2022-03-11 18:09:22 -06:00
Ross Thompson
d68446cf92 Added new asserts to testbench. 2022-03-11 15:41:53 -06:00
Ross Thompson
e802deb4d6 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
Ross Thompson
3dbf6790e1 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Ross Thompson
81a2fbb6d2 mild cleanup. 2022-03-11 13:05:47 -06:00
Ross Thompson
11e5aad38a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
Ross Thompson
a12016e69b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
04dd2f0eb5 atomic cleanup. 2022-03-10 18:56:37 -06:00
Ross Thompson
a598760445 Name changes. 2022-03-10 18:50:03 -06:00
Ross Thompson
bdfca503fa Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
5c16b65a16 simplified uncore's name for HWDATA. 2022-03-10 18:17:44 -06:00
Ross Thompson
543e10ab32 Moved subwordwrite to lsu directory. 2022-03-10 18:15:25 -06:00
Ross Thompson
54abd944e2 Simplified byte write enable logic. 2022-03-10 18:13:35 -06:00
Ross Thompson
50789f9ddd Byte write enables are passing all configs now. 2022-03-10 17:26:32 -06:00
Ross Thompson
f7df3a0666 Progress on the path to getting all configs working with byte write enables. 2022-03-10 17:02:52 -06:00
Ross Thompson
83133f8c47 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
d5f524a15e Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
David Harris
b1340653cf bit write update 2022-03-09 19:09:20 +00:00
David Harris
004853c312 Refactored SRAM bit write enable 2022-03-09 17:49:28 +00:00
David Harris
ba9320d822 Updated testbench to read expected flags 2022-03-09 13:58:17 +00:00
Ross Thompson
2a8a1cd191 Minor cleanup to interlockfsm. 2022-03-08 23:38:58 -06:00
Ross Thompson
ac9528b450 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-08 18:05:35 -06:00
Ross Thompson
ed32801cc1 Comments. 2022-03-08 18:05:25 -06:00
Ross Thompson
534fd70f76 Marked signals for name changes. 2022-03-08 17:41:02 -06:00
David Harris
5d0b9bab6e Added more test cases and rounding modes to fma test generator 2022-03-08 23:29:29 +00:00
David Harris
582b943380 fixed setup.sh merge conflict 2022-03-08 23:21:06 +00:00
David Harris
cfa82efccc fma16_testgen.c test cases 2022-03-08 23:18:18 +00:00
Ross Thompson
acd60218b8 Removed unused signal. 2022-03-08 16:58:26 -06:00
Ross Thompson
cc21414051 Added parameter to spillsupport. 2022-03-08 16:38:48 -06:00
Ross Thompson
60e6c1ffa7 Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
bbracker
51e68819c4 fix up PLIC and UART checkpointing 2022-03-07 23:48:47 -08:00
bbracker
c2ac18b5de change testbench-linux.sv to use new shared location of disassembly files 2022-03-07 20:04:08 -08:00
David Harris
d2282d5e87 Checked in fma16_template.v 2022-03-06 13:29:35 +00:00
David Harris
9fd861a9ee removed more old 64priv tests 2022-03-04 03:57:19 +00:00
bbracker
51f1a411dd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:12:00 +00:00
bbracker
1c5697874f comment out nonfunctioning CSR-PERMISSIONS-M test 2022-03-04 00:11:55 +00:00
David Harris
63e9d846e4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:07:34 +00:00
David Harris
48705457d5 LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
bbracker
efb5d1dbc0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:06:27 +00:00
bbracker
443dd40ea8 remove imperas32p tests 2022-03-04 00:06:18 +00:00
David Harris
545f569f78 Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
David Harris
080fef6436 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-02 23:47:16 +00:00
David Harris
8fbdbba81a fma file fixes 2022-03-02 23:47:01 +00:00
bbracker
e28ca531e0 fix peripheral test and add it to regression 2022-03-02 23:44:39 +00:00
bbracker
be2f668867 but apparently QEMU doesn't show UXL in SSTATUS 2022-03-02 22:44:19 +00:00
bbracker
01e0f2f0d2 update SXL UXL bits in MSTATUS to match new QEMU trace 2022-03-02 22:15:57 +00:00
bbracker
c1290d493f add CSRs to waveview 2022-03-02 18:31:10 +00:00
bbracker
d7b8c9d877 add rv32a tests to regression 2022-03-02 17:54:55 +00:00
bbracker
6c422cd357 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-02 17:46:40 +00:00
David Harris
3bea7bb431 removed imperas-riscv-tests 2022-03-02 17:28:20 +00:00
bbracker
5f5cc514b8 fix buildroot checkpointing and add it back to regression 2022-03-02 16:00:19 +00:00
bbracker
4f22a55dd4 add LRSC test and add wally64a to regression 2022-03-02 07:09:37 +00:00
David Harris
1661983345 FMA project ready to start 2022-03-01 20:58:08 +00:00
bbracker
41b3912abc buildroot graphical sim bugfix 2022-03-01 03:24:23 +00:00
bbracker
04ace8c154 switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv 2022-03-01 03:11:43 +00:00
bbracker
d620fb4442 deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test 2022-03-01 00:37:46 +00:00
David Harris
f314e60dc8 Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
David Harris
f0a7ae2bba adrdecs comments 2022-02-28 20:33:41 +00:00
David Harris
e108eb5195 Modified address decoder for native access to CLINT 2022-02-28 19:13:14 +00:00
David Harris
3519a20ccf hptw cleanup for synthesis 2022-02-28 05:54:34 +00:00
David Harris
bb14dba9be Created softfloat_demo showcasing how to do math with SoftFloat 2022-02-27 18:17:21 +00:00
David Harris
046259cff8 Moved regression work directories to regression/wkdir to reduce clutter 2022-02-27 17:35:09 +00:00
David Harris
c7b5d32a72 Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior 2022-02-27 17:23:33 +00:00
David Harris
c6561d1e8b Moved FMA back into source tree to facilitate synthesis 2022-02-27 15:41:41 +00:00
David Harris
eb0bbacd43 Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue 2022-02-27 15:12:10 +00:00
David Harris
274ecf13ad Moved fma directory 2022-02-27 14:20:15 +00:00
David Harris
5a5142c14f fma simulation infrastructure 2022-02-27 04:36:43 +00:00
David Harris
d917cc1379 fma passing multiply vectors 2022-02-27 04:36:01 +00:00
David Harris
8a55935456 simplified fma Makefile 2022-02-26 19:55:42 +00:00
David Harris
1852eccaab Made softfloat.a a symlink 2022-02-26 19:53:04 +00:00
David Harris
87d1a8a1ac Added start of fma 2022-02-26 19:51:19 +00:00
David Harris
eda60a7691 Moved Softfloat / TestFloat 2022-02-26 19:17:32 +00:00
Ross Thompson
97d64201f7 Fixed bug with DAPageFault being wrong when HPTW writes not supported. 2022-02-23 10:54:34 -06:00
Ross Thompson
53f13d4cbc More spillsupport more structual. 2022-02-23 10:27:14 -06:00
Ross Thompson
c23f6c7d90 Fixed bug with spill support and Instruction DA Page Faults. 2022-02-23 10:16:12 -06:00
Ross Thompson
62e1a97287 Added generates to pcnextf muxes for privileged and caches. 2022-02-22 22:45:00 -06:00
Ross Thompson
d331b9f29d Fixed "bug" with wally-pipelined.do 2022-02-22 22:19:25 -06:00
Ross Thompson
6a52f95cc8 Minor busdp cleanup. 2022-02-22 17:28:26 -06:00
Ross Thompson
59a2c09c5e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-22 14:45:53 -06:00
Ross Thompson
90be3d4360 Clarified interlockfsm. 2022-02-22 11:31:28 -06:00
bbracker
b8fd06576c fix lint bugs in PLIC and UART 2022-02-22 05:04:18 +00:00
bbracker
a6047697c3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-22 04:27:50 +00:00
bbracker
6caa97bb26 change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests 2022-02-22 03:46:08 +00:00
bbracker
e7934c585a change RX side of UART to aslo be LSB-first 2022-02-22 03:34:08 +00:00
Ross Thompson
3a29504279 Added some clearity to lsuvirtmem.sv. 2022-02-21 17:20:58 -06:00
Ross Thompson
ca59778c5a Annotated IFU for mux changes. 2022-02-21 17:20:34 -06:00
Ross Thompson
2f711fb642 Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW. 2022-02-21 16:54:38 -06:00
Ross Thompson
0c65ea96d8 Cleaned up names in lsuvirtmem. 2022-02-21 16:44:30 -06:00
Ross Thompson
a6e83a2ca2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-21 12:46:22 -06:00
Ross Thompson
56fc6d0d7c Minor cleanup of lsu. 2022-02-21 12:46:06 -06:00
ushakya22
67780305ae Moved order of reading a, b, and result from test vectors file so that result 
matches up with inputs a and b
 2022-02-21 17:28:11 +00:00
ushakya22
88060a74f5 - created new testbench file instead of having it at the bottom of the srt file 
- uses unpacker to parse 64 bit floating point numbers
- updated testbench to read from new testvectors generated by exptestbench

Notes:
MEM_WIDTH updated to be 64*3
Input numbers and output result is 64 bit number
MEM_SIZE set to 60000
 2022-02-21 16:24:50 +00:00
ushakya22
d1089163a9 - Created exponent divsion module 
- top module includes exponent module now

Notes:
- may be a better implementation of the exponent module rather than
having what I believe are two adders currently
 2022-02-21 16:13:30 +00:00
ushakya22
c6bd51a707 Changed Makefile to compile exptestgen instead of testgen 2022-02-21 16:08:45 +00:00
ushakya22
08d997d68b reverted srt_standford back to original file pre modifications by Udeema 2022-02-21 16:08:09 +00:00
ushakya22
1495f6ac70 verilator lint for srt 2022-02-21 16:05:43 +00:00