David Harris
ddba68605e
Renamed DivBusy to FDivBusyE in FPU
2022-11-16 10:13:27 -08:00
David Harris
e008d663f4
Moved DivStartE to fdivsqrtfsm
2022-11-16 10:00:07 -08:00
Ross Thompson
900a326a23
Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
2022-11-16 11:15:34 -06:00
cturek
6fe35ee0e3
Attempt to fix FPGA synth errors
2022-11-15 20:34:28 +00:00
cturek
1c49d4a1c2
Fixed lint errors in postprocessing
2022-11-15 20:31:23 +00:00
Ross Thompson
ec6517fadd
Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.
2022-11-14 16:02:20 -06:00
Ross Thompson
f03d5d3ac8
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
1bf838fa6b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 13:48:56 -06:00
David Harris
895ee3d773
Removed comment about nonexistent possible bug
2022-11-14 09:56:33 -08:00
David Harris
cae3e00751
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 09:52:24 -08:00
David Harris
79d416537a
Removed comment about nonexistent possible bug
2022-11-14 09:52:21 -08:00
Ross Thompson
1a00e7bbee
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
cturek
0b2c8b9d46
Added majority of combinational logic
2022-11-14 00:06:38 +00:00
cturek
74f58b5d89
Added Quotient/Remainder calcs to normal termination
2022-11-13 23:44:34 +00:00
cturek
b3bfdbad18
Added flops for n and m, added B=0 signal
2022-11-13 23:02:43 +00:00
cturek
9c70ab917c
Added A<B signal to fdivsqrt, started postprocessing merge
2022-11-13 22:40:26 +00:00
Ross Thompson
a27b81ef90
Changed IMWriteDataM to IHWriteDataM.
2022-11-13 12:27:48 -06:00
Ross Thompson
3ac6514856
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
hazard was not a straight forward merge. I changed the way the LSU and IFU generate IFUStallF and LSUStallM. They need to be suppressed by TrapM now.
2022-11-13 12:25:22 -06:00
David Harris
0ce3cc393a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-13 04:23:26 -08:00
David Harris
157f816cd3
HPTW cleanup
2022-11-13 04:23:23 -08:00
David Harris
0502b8ea4d
Comments about division hazards
2022-11-13 04:17:37 -08:00
Ross Thompson
90697ef888
Moved all remaining bus logic from the LSU into ahbcacheinterface.
2022-11-11 14:30:32 -06:00
cturek
ff410cd849
Added integer step counter to fsm
2022-11-11 00:23:25 +00:00
Ross Thompson
c2e3bad3f5
Fixed name change in hptw.
2022-11-10 16:13:31 -06:00
Ross Thompson
64b818c49a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-10 15:46:25 -06:00
Ross Thompson
31d5eabd77
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
3653d6b3ed
Renamed CACHE_EVICT to CACHE_WRITEBACK.
2022-11-09 17:43:06 -06:00
cturek
e7c25f9562
Fixed asign and bsign
2022-11-09 18:41:26 +00:00
Ross Thompson
42c0a10d07
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
David Harris
9b20bf341e
Moved lsuvirtmem muxes into hptw
2022-11-07 11:13:34 -08:00
Ross Thompson
922513c22f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-07 09:10:51 -06:00
cturek
b137a95a35
propagated otfc swap to Rad2 and 4 qslc
2022-11-06 23:32:38 +00:00
Ross Thompson
8d57e488c8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-06 17:22:25 -06:00
cturek
1e927df1a0
Added conditional OTFC swap for simplified int postprocessing
2022-11-06 23:09:09 +00:00
cturek
56b7bb3590
Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv
2022-11-06 22:40:21 +00:00
cturek
ee048325cb
Added n and rightshiftx
2022-11-06 22:31:48 +00:00
cturek
67f2cb0595
p calculation
2022-11-06 22:24:21 +00:00
cturek
7567f388c2
Changed lzc names, started int/fp size merge in preproc
2022-11-06 22:21:35 +00:00
cturek
333da5c945
Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
2022-11-06 22:08:18 +00:00
cturek
b893d9249d
Added new macros for int div preprocessing, added p, n, and rightshiftx logic
2022-11-06 21:53:48 +00:00
David Harris
e57083a0ef
HPTW cleanup
2022-11-04 15:21:09 -07:00
Ross Thompson
977ad1c33c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-04 13:30:08 -05:00
cturek
39bf6a456e
renamed remOp to RemOp
2022-11-03 22:37:25 +00:00
cturek
890b26466f
Added rem/div operation to postprocessor
2022-11-02 17:49:40 +00:00
Ross Thompson
98d4929c57
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
cturek
2a45787b37
Added buffered signals for int/fp
2022-10-28 21:47:24 +00:00
cturek
2ae0a9bb5d
Config Cleanup
2022-10-27 22:38:56 +00:00
Ross Thompson
03f68a4cf5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-26 14:48:50 -05:00
Ross Thompson
36d9a00471
Fixed the uart transmit fifo overrun bug.
2022-10-26 14:48:09 -05:00
cturek
51fc4de0e1
small signal cleanup
2022-10-26 18:42:49 +00:00
cturek
544c142c4f
abs for int inputs
2022-10-26 16:18:05 +00:00
cturek
e401d12889
Added signed division to fdivsqrt
2022-10-26 16:13:41 +00:00
Jacob Pease
ec0cede2f2
Added PLIC signals for debugging on FPGA.
2022-10-25 13:57:09 -05:00
cturek
94daa961b3
Started Integer Preprocessing
2022-10-25 17:48:43 +00:00
Ross Thompson
1510c2d92f
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
cc605a1966
Bit width error.
2022-10-24 13:48:47 -05:00
Ross Thompson
270a83352f
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
54bd1fb806
Small cleanup of interlockfsm.
2022-10-22 16:29:51 -05:00
Ross Thompson
f9a04c13df
comment updates.
2022-10-22 16:28:44 -05:00
Ross Thompson
78586c5a7a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-22 16:27:30 -05:00
Ross Thompson
611ea6882d
Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.
2022-10-22 16:27:20 -05:00
Jacob Pease
1f207bcafb
Extended rxfifotimeout count to actually be 4 characters long.
2022-10-20 17:35:49 -05:00
Ross Thompson
e5cae3bfa0
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
5ad3ee6b54
Broken don't use this state.
2022-10-19 14:31:22 -05:00
Ross Thompson
de1e569ee9
Noted possible bug with endianness during hptw.
...
Minor complexity reduction in interlockfsm. I think there is a lot of room to simplify.
2022-10-19 12:20:19 -05:00
Ross Thompson
61f7bad739
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-18 15:06:09 -05:00
Ross Thompson
962ba5e4b8
Updated uart settings and fpga wave config.
2022-10-18 15:05:33 -05:00
Ross Thompson
a7ae593a68
Possible fix for interrupt during a floating point divide.
2022-10-18 15:04:21 -05:00
Ross Thompson
2c80c2b35f
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
amaiuolo
a0712d1456
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-10-13 22:36:57 +00:00
amaiuolo
000117fcd4
added amaiuolo@hmc.edu
2022-10-13 22:36:52 +00:00
Ross Thompson
47915421c2
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
fccaad7f3f
Fixed LSU to correctly handle the difference between LLEN and AHBW.
2022-10-12 12:06:15 -05:00
Ross Thompson
12a6a9f83b
Actually fixed the bus width issue coming out of the cache.
...
The root cause is the ahb bus width can be different from LLEN.
If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well.
Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.
2022-10-12 11:33:10 -05:00
Kip Macsai-Goren
f711eb0bcf
quick fix to endianness wapping 64 bit reads in 32 bit confgs
2022-10-11 23:08:02 +00:00
Ross Thompson
b2f71b8255
Modified LSU to support DTIM without CSRs.
2022-10-11 14:05:20 -05:00
Ross Thompson
a5c15fd801
Fixed first problem with the rv64i IROM.
2022-10-11 11:35:40 -05:00
David Harris
36c0e1d4e9
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
e4c5754b3a
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
David Harris
a5a922d048
Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing
2022-10-10 07:12:37 -07:00
David Harris
6092ca757a
New fdivsqrtqsel4cmp module based on comparators rather than table lookup
2022-10-09 04:47:44 -07:00
David Harris
dceb6f9034
Moved shift into divsqrt stage and cleaned up comments
2022-10-09 04:45:45 -07:00
David Harris
55e4911cf0
fdivsqrt code cleanup
2022-10-09 03:37:27 -07:00
Ross Thompson
382ccf74a5
Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.
2022-10-05 15:46:53 -05:00
Ross Thompson
62951ec653
Fixed wally32e.
2022-10-05 15:37:01 -05:00
Ross Thompson
2144343c4a
Name clarifications.
2022-10-05 15:36:56 -05:00
Ross Thompson
2e578eb8d8
Fixed bug with combined dtim+bus.
2022-10-05 15:16:01 -05:00
Ross Thompson
b52ab91028
Possibly have working dtim + bus config.
2022-10-05 15:08:20 -05:00
Ross Thompson
a0c5833d6d
Fixed bug in EBU.
2022-10-05 14:51:12 -05:00
Ross Thompson
68aa1434b4
Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.
...
Don't use this commit as the rv32i tests are not passing.
2022-10-05 14:51:02 -05:00
Ross Thompson
e6b36d0c02
Optimized the ebu's beat counting.
2022-10-05 10:58:23 -05:00
Ross Thompson
3f59ea6b6d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-04 17:38:49 -05:00
Ross Thompson
92d7be645b
Reordered the eviction and fetch in cache so it follows a more logical order.
2022-10-04 17:36:07 -05:00
Ross Thompson
52e8e0f5ef
Modified cache lru to not have the delayed write.
2022-10-04 15:14:58 -05:00
Kip Macsai-Goren
2bbcec680f
addded renamed file
2022-10-04 17:37:05 +00:00
Kip Macsai-Goren
c4441eb0fa
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
175e824a61
Renamed endianswap to match module name
2022-10-04 17:33:49 +00:00
Ross Thompson
56cc04316c
Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
2022-10-02 16:21:21 -05:00
Ross Thompson
02ed8fc301
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-01 15:01:22 -05:00
Ross Thompson
bc94f4aef1
Disable IFU bus access on TrapM.
2022-10-01 14:54:16 -05:00
