Ross Thompson 1a00e7bbee Changed names of cache signals.		2022-11-13 21:36:12 -06:00
..
cache	Changed names of cache signals.	2022-11-13 21:36:12 -06:00
ebu	Moved all remaining bus logic from the LSU into ahbcacheinterface.	2022-11-11 14:30:32 -06:00
fpu	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-13 04:23:26 -08:00
generic	Changed names of cache signals.	2022-11-13 21:36:12 -06:00
hazard	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-13 12:25:22 -06:00
ieu	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
ifu	Changed names of cache signals.	2022-11-13 21:36:12 -06:00
lsu	Changed names of cache signals.	2022-11-13 21:36:12 -06:00
mmu	Changed IMWriteDataM to IHWriteDataM.	2022-11-13 12:27:48 -06:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.	2022-10-02 16:21:21 -05:00
uncore	Fixed the uart transmit fifo overrun bug.	2022-10-26 14:48:09 -05:00
wally	Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).	2022-11-07 15:50:55 -06:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00