David Harris
|
7151befd04
|
Removed FStore2 and simplified HPTW
|
2022-08-22 13:29:54 -07:00 |
|
David Harris
|
bf54c1c868
|
Simplified FPU-LSU interface to skip IEU
|
2022-08-22 13:29:20 -07:00 |
|
David Harris
|
fffad8b314
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-22 13:28:54 -07:00 |
|
David Harris
|
2170203847
|
Simplified FPU-LSU interface to skip IEU
|
2022-08-22 13:28:51 -07:00 |
|
Katherine Parry
|
a1f0c6c598
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-08-22 17:16:25 +00:00 |
|
Katherine Parry
|
1accb92745
|
sqrt passes - lint warnings remain
|
2022-08-22 17:16:12 +00:00 |
|
David Harris
|
564281b8c1
|
Removed 2-cycle FPU-IEU latency stall
|
2022-08-22 16:14:15 +00:00 |
|
David Harris
|
1404d1c248
|
moved CSA to generic
|
2022-08-22 08:41:23 +00:00 |
|
David Harris
|
a8870b70b2
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-08-22 08:28:31 +00:00 |
|
David Harris
|
b91f33372e
|
Commented out unused comparators
|
2022-08-22 08:28:28 +00:00 |
|
Ross Thompson
|
88d34d0f56
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-21 16:03:11 -05:00 |
|
Ross Thompson
|
21526957cf
|
Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
|
2022-08-21 15:59:54 -05:00 |
|
Ross Thompson
|
92c3cdc27d
|
Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.
|
2022-08-21 15:28:29 -05:00 |
|
Ross Thompson
|
a049f456e8
|
Removed logic from Verilog wrapper.
|
2022-08-21 14:07:43 -05:00 |
|
Ross Thompson
|
dad6770fc3
|
Updated fpga testbench.
|
2022-08-21 14:07:26 -05:00 |
|
Katherine Parry
|
617dc02d01
|
fixed -1 issue in division
|
2022-08-20 00:53:45 +00:00 |
|
Ross Thompson
|
96d6218078
|
Possible reduction of ignorerequest.
|
2022-08-19 18:07:44 -05:00 |
|
Ross Thompson
|
5301444a61
|
Changed signal names.
|
2022-08-17 16:12:04 -05:00 |
|
Ross Thompson
|
970a90dd72
|
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
|
2022-08-17 16:09:20 -05:00 |
|
Ross Thompson
|
c3bd396bdb
|
Removed old code from interlockfsm.
|
2022-08-17 12:52:56 -05:00 |
|
Katherine Parry
|
0f077012c3
|
sqrt tests in regression uncommented and pass
|
2022-08-07 23:38:10 +00:00 |
|
Katherine Parry
|
8eeca3319c
|
radix-2 1 copy passes testfloat
|
2022-08-06 22:54:05 +00:00 |
|
Katherine Parry
|
8f1d8669b0
|
fixed fsw problem and removed 2 bit shift from shift correction
|
2022-08-03 22:16:51 +00:00 |
|
David Harris
|
8b8f045491
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
|
2022-08-03 09:33:56 -07:00 |
|
David Harris
|
6ee8036ae7
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
b13cdf79b3
|
FMA cleanup
|
2022-08-02 07:42:32 -07:00 |
|
David Harris
|
baeafc4fd2
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-02 07:34:12 -07:00 |
|
David Harris
|
d3e39763b6
|
Moved InvA to sign block; simplified fmaexpadd coding
|
2022-08-02 07:34:09 -07:00 |
|
Ross Thompson
|
acd920ae2f
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-01 22:09:11 -05:00 |
|
Ross Thompson
|
f7e64fcd69
|
Fixed fstore2 in cache?
|
2022-08-01 22:04:44 -05:00 |
|
David Harris
|
0482bf4fc0
|
merged lza back into main
|
2022-08-01 19:45:21 -07:00 |
|
David Harris
|
0b95ca129c
|
Fixed fmaadd to work with new LZA
|
2022-08-01 19:40:55 -07:00 |
|
Ross Thompson
|
b8356c7449
|
Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
|
2022-08-01 21:12:25 -05:00 |
|
Ross Thompson
|
171cf7413b
|
Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
|
2022-08-01 21:08:14 -05:00 |
|
Ross Thompson
|
5d9dab6149
|
pulled swbbytemask out of subword write.
|
2022-08-01 20:48:45 -05:00 |
|
David Harris
|
8b44037f58
|
Parameterized fmalza
|
2022-08-01 16:18:02 -07:00 |
|
David Harris
|
6e78b46761
|
Completed LZA simplificaiton
|
2022-08-01 16:13:16 -07:00 |
|
David Harris
|
76021769a7
|
lza cleanup
|
2022-08-01 16:01:02 -07:00 |
|
David Harris
|
47d204f4a2
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-01 15:47:58 -07:00 |
|
David Harris
|
c8d4f3a542
|
lza cleanup
|
2022-08-01 15:47:03 -07:00 |
|
David Harris
|
c531df9c4e
|
lza cleanup
|
2022-08-01 15:43:48 -07:00 |
|
David Harris
|
5468a90cf3
|
lza cleanup
|
2022-08-01 15:40:12 -07:00 |
|
David Harris
|
4953ccf273
|
lza cleanup
|
2022-08-01 15:37:09 -07:00 |
|
Katherine Parry
|
66eca28ccd
|
regression passes fpu tests
|
2022-08-01 19:56:25 +00:00 |
|
Katherine Parry
|
9672f5451a
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-08-01 19:55:50 +00:00 |
|
David Harris
|
31215277ee
|
more lza cleanup
|
2022-08-01 12:34:00 -07:00 |
|
David Harris
|
48500c642c
|
LZA cleanup
|
2022-08-01 12:30:42 -07:00 |
|
David Harris
|
87e6402af6
|
LZA refactoring switched to Pp1, Gm1, Km1
|
2022-08-01 12:20:23 -07:00 |
|
David Harris
|
5012b96120
|
LZA refactoring
|
2022-08-01 11:36:21 -07:00 |
|
Katherine Parry
|
75f39e0c5b
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-08-01 18:35:07 +00:00 |
|
David Harris
|
231f52c1fd
|
fmalza edits to match textbook
|
2022-08-01 18:23:39 +00:00 |
|
David Harris
|
e3b970d3ff
|
Partitioned fma into separate files
|
2022-08-01 18:07:38 +00:00 |
|
Ross Thompson
|
01359dbc4b
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-31 12:48:51 -05:00 |
|
Katherine Parry
|
de03954946
|
re-added FStore2 in Cache
|
2022-07-29 22:54:49 +00:00 |
|
David Harris
|
d2de84a456
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
|
David Harris
|
da275e3c26
|
Increased timeout threshold to avoid timeout building riscof tests on slow machine
|
2022-07-27 04:05:21 +00:00 |
|
David Harris
|
ae4ea00ff0
|
fixed testbench merge comflict
|
2022-07-26 06:21:46 -07:00 |
|
David Harris
|
449c80b5f7
|
More work toward riscof tests
|
2022-07-26 06:19:13 -07:00 |
|
David Harris
|
094aacdf6f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-25 23:29:08 +00:00 |
|
David Harris
|
ccf8ccfa24
|
Added rv32f tests to RV64gc
|
2022-07-25 23:29:05 +00:00 |
|
David Harris
|
539174f6f6
|
Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
|
2022-07-25 16:23:10 -07:00 |
|
David Harris
|
55ab81e37b
|
More riscof makefile tuning
|
2022-07-25 21:15:56 +00:00 |
|
David Harris
|
6b172723bd
|
Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings
|
2022-07-25 20:50:38 +00:00 |
|
Ross Thompson
|
f1bd2524b7
|
Don't use this commit yet. Untested.
|
2022-07-24 15:40:52 -05:00 |
|
Ross Thompson
|
334008630f
|
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
|
2022-07-24 01:20:29 -05:00 |
|
Ross Thompson
|
856ac24686
|
Removed replay from the config files.
|
2022-07-24 00:34:11 -05:00 |
|
Ross Thompson
|
e12e6c3acd
|
Added more i-cache signals to wave file.
|
2022-07-24 00:24:13 -05:00 |
|
Ross Thompson
|
458bfbf6f6
|
Merged evict dirty clear with flush write back.
|
2022-07-24 00:22:43 -05:00 |
|
Ross Thompson
|
70032bf8f4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-23 08:41:59 -05:00 |
|
Ross Thompson
|
5cd6c8069d
|
signal name cleanup.
|
2022-07-22 23:36:27 -05:00 |
|
Ross Thompson
|
7d026e02f2
|
cache cleanup after removing replay on cpubusy.
|
2022-07-22 23:30:25 -05:00 |
|
Ross Thompson
|
706bc819e1
|
cache fsm cleanup after removal of replay.
|
2022-07-22 23:25:09 -05:00 |
|
Ross Thompson
|
0f586c9ed3
|
Possible improvement to cache which removes the cpu_busy states.
|
2022-07-22 23:20:37 -05:00 |
|
Katherine Parry
|
bd336f18b3
|
merged radix-2 sqrt into divider - doesnt work yet
|
2022-07-23 00:41:18 +00:00 |
|
slmnemo
|
5b71ceac5c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-22 17:13:38 -07:00 |
|
slmnemo
|
0bfc3fda1b
|
Fixed UART FIFO bugs and added FIFO tests
|
2022-07-22 17:13:19 -07:00 |
|
Daniel Torres
|
b726b05d61
|
fixed wally rv32e tests, updated regression makefile to new testflow
|
2022-07-22 17:09:46 -07:00 |
|
Katherine Parry
|
ee7932c804
|
divider sizes reworked to match book
|
2022-07-22 22:02:04 +00:00 |
|
Daniel Torres
|
d95b266d49
|
changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
|
Daniel Torres
|
2bbfd67082
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
|
2022-07-22 14:58:55 -07:00 |
|
slmnemo
|
44c30ec082
|
fixed error in tests.vh
|
2022-07-22 14:55:55 -07:00 |
|
slmnemo
|
170601af0b
|
Added UART test to peripheral test
|
2022-07-22 14:55:34 -07:00 |
|
Daniel Torres
|
fbe3a1af12
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-22 13:52:19 -07:00 |
|
Daniel Torres
|
261b9aa5a1
|
commented out embench test that should be commented out
|
2022-07-22 13:52:13 -07:00 |
|
slmnemo
|
49329b3f42
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-22 12:36:06 -07:00 |
|
slmnemo
|
0d98ff74b4
|
Added PLIC test to regression
|
2022-07-22 12:35:37 -07:00 |
|
Daniel Torres
|
5d7171f6f8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-22 11:16:09 -07:00 |
|
Daniel Torres
|
526f70e772
|
commiting current changes to riscof wally tests
|
2022-07-22 11:14:04 -07:00 |
|
cturek
|
338f44dfc8
|
Square root negative exponent handling
|
2022-07-22 16:45:19 +00:00 |
|
slmnemo
|
49565f944c
|
Added PLIC and UART tests and new functions to the test library
|
2022-07-22 07:10:39 -07:00 |
|
David Harris
|
07c946bb04
|
Reset MSR on read
|
2022-07-22 04:29:27 +00:00 |
|
Daniel Torres
|
f1578936b8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-21 20:59:01 -07:00 |
|
Daniel Torres
|
bd918d37ba
|
added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
|
2022-07-21 20:58:58 -07:00 |
|
slmnemo
|
99dcff80c9
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-21 20:35:52 -07:00 |
|
slmnemo
|
bfa500234d
|
Fixed UART bug related to parity and MSR/LSR
|
2022-07-21 20:35:46 -07:00 |
|
cturek
|
c170a8d9b6
|
Changed testbench to operate on two inputs and one output, changed all test generators, changed srt module to return only one output and take in Mod as a signal to compute integer remainder
|
2022-07-22 01:27:08 +00:00 |
|
cturek
|
abe1ff906e
|
Renamed variables, moved output handling to postprocessor, added remainder handling
|
2022-07-21 20:45:08 +00:00 |
|
Daniel Torres
|
a17361870f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-21 12:50:04 -07:00 |
|
Daniel Torres
|
6e9b4f4075
|
removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
|
2022-07-21 12:47:51 -07:00 |
|
Katherine Parry
|
e330a840b0
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-21 19:38:15 +00:00 |
|
Katherine Parry
|
270216dd02
|
radix-4 division integrated into srt - not tested
|
2022-07-21 19:38:06 +00:00 |
|
cturek
|
ddc237f6bc
|
Division working too
|
2022-07-21 17:59:10 +00:00 |
|
cturek
|
9c694b887e
|
Updated Radix2 Sqrt to follow new algorithm
|
2022-07-21 17:36:21 +00:00 |
|
Katherine Parry
|
67c99d3d1a
|
added input enables and improved forwarding
|
2022-07-21 01:20:06 +00:00 |
|
Katherine Parry
|
e8c9830b88
|
turn off 2 word store durring non-fp instructions
|
2022-07-20 21:57:23 +00:00 |
|
Ross Thompson
|
9868e685a4
|
Minor cleanup of cache.
|
2022-07-19 23:04:23 -05:00 |
|
Ross Thompson
|
6c8ac7851e
|
Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
|
2022-07-19 22:42:25 -05:00 |
|
Katherine Parry
|
fb890d621d
|
moved ctrl signal registers into fctrl, also a lot of code cleaning
|
2022-07-20 02:27:39 +00:00 |
|
cturek
|
d7e90a7086
|
divsqrt working for floating point
|
2022-07-20 02:04:20 +00:00 |
|
cturek
|
8e66b81821
|
New radix-2 algorithm implemented and working
|
2022-07-20 02:00:43 +00:00 |
|
cturek
|
db39a05abc
|
small changes
|
2022-07-20 01:36:25 +00:00 |
|
Katherine Parry
|
531829f7c8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-19 23:44:41 +00:00 |
|
Katherine Parry
|
afcddf7035
|
oprimized zeros and replaced complex ?: with always_comb
|
2022-07-19 23:44:37 +00:00 |
|
Daniel Torres
|
d33d0d22bd
|
commented out embench 2.0 tests
|
2022-07-19 13:36:18 -07:00 |
|
Ross Thompson
|
ffda64587c
|
Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
|
2022-07-18 23:37:18 -05:00 |
|
Katherine Parry
|
4c2afbbc4f
|
moved Se into execute stage
|
2022-07-19 01:10:10 +00:00 |
|
Katherine Parry
|
a590728350
|
reworked fmashiftcalc to match book
|
2022-07-19 00:04:24 +00:00 |
|
David Harris
|
59eb11b73a
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-18 23:11:12 +00:00 |
|
Katherine Parry
|
e599f82b29
|
moved Ss to execute stage
|
2022-07-18 20:48:56 +00:00 |
|
Katherine Parry
|
921debf930
|
removed underflow from inexactct calculation
|
2022-07-18 17:51:18 +00:00 |
|
Katherine Parry
|
ea7b32a50b
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-18 17:31:29 +00:00 |
|
Katherine Parry
|
5bb1478859
|
renamed signals in ocde to match book
|
2022-07-18 17:31:17 +00:00 |
|
Ross Thompson
|
a88543275f
|
Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
|
2022-07-17 21:05:31 -05:00 |
|
Ross Thompson
|
3670c47141
|
Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
|
2022-07-17 16:20:04 -05:00 |
|
David Harris
|
7c744f0053
|
Rewrote convert shift calculation with always for ease of reading
|
2022-07-17 16:40:58 +00:00 |
|
David Harris
|
6e1d4ec4ed
|
restored intPending logic to be sticky for PLIC
|
2022-07-16 17:43:31 -07:00 |
|
Katherine Parry
|
a4cd157f00
|
forgot some files
|
2022-07-15 21:42:45 +00:00 |
|
Katherine Parry
|
e498d87c5c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-15 20:17:08 +00:00 |
|
Katherine Parry
|
e251022269
|
merged floating-point radix-2 divider with radix-4
|
2022-07-15 20:16:59 +00:00 |
|
cturek
|
ec9536f983
|
Square root radix 2 working, does not work with division
|
2022-07-14 22:52:09 +00:00 |
|
cturek
|
9f18f6a203
|
Square root
|
2022-07-14 21:19:45 +00:00 |
|
cturek
|
38bbd19abf
|
Six tests passing and a bunch of sizizing issues fixed
|
2022-07-14 19:38:27 +00:00 |
|
Katherine Parry
|
a0e9e93d4f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-14 18:16:13 +00:00 |
|
Katherine Parry
|
b069cfbec2
|
fixed error in divsqrt
|
2022-07-14 18:16:00 +00:00 |
|
cturek
|
f49c2a969f
|
S and SM are updating but are not correct yet
|
2022-07-14 00:39:30 +00:00 |
|
Katherine Parry
|
e5a8ac2a44
|
renamed a file to fit diagram
|
2022-07-13 23:44:54 +00:00 |
|
cturek
|
7629173b15
|
DIVLEN and counter updated for sqrt computation and rounding
|
2022-07-13 22:42:39 +00:00 |
|
Katherine Parry
|
7e163e22a3
|
some code cleanup
|
2022-07-13 15:28:22 -07:00 |
|
Katherine Parry
|
77ea4e47cb
|
removed minus 1 case in rounding
|
2022-07-13 15:01:38 -07:00 |
|
cturek
|
d57fb6f98a
|
radix 4 files removed from srt and divlen modified for sqrt
|
2022-07-13 19:46:48 +00:00 |
|
cturek
|
9b7e63f482
|
Lint error fixed and added comments to preprocessing
|
2022-07-13 19:34:04 +00:00 |
|
cturek
|
81f396f885
|
Testbench accepts standard test vector files
|
2022-07-13 18:30:18 +00:00 |
|
cturek
|
11bb3f0a3e
|
Test generation files in common format
|
2022-07-13 18:11:13 +00:00 |
|
cturek
|
110b762b55
|
Finalized sqrt, ready for debugging
|
2022-07-13 17:56:23 +00:00 |
|
cturek
|
31db938e7e
|
Added adder input selection to on the fly converter
|
2022-07-13 17:47:27 +00:00 |
|
cturek
|
bb7e73abf0
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-13 17:36:56 +00:00 |
|
Katherine Parry
|
26e39dd325
|
removed the +1 in the cvt
|
2022-07-13 09:41:35 -07:00 |
|
Katherine Parry
|
e05b2a07d2
|
removed warnings and took a mux out of the critical path
|
2022-07-12 18:32:17 -07:00 |
|
cturek
|
5c9f011561
|
little fix
|
2022-07-12 23:04:33 +00:00 |
|
cturek
|
ed9106128f
|
Square root implemented
|
2022-07-12 22:45:54 +00:00 |
|
Katherine Parry
|
452b017f9a
|
found the bug in the store modification
|
2022-07-12 22:42:19 +00:00 |
|
Katherine Parry
|
2ada8a8bc1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-12 22:37:20 +00:00 |
|
cturek
|
9d4acc9ddb
|
C register and other various fixes
|
2022-07-12 22:18:56 +00:00 |
|
cturek
|
3483b92480
|
On the fly conversion for square root
|
2022-07-12 02:21:38 +00:00 |
|
Katherine Parry
|
5c0ecfa433
|
forgot a file
|
2022-07-11 18:31:51 -07:00 |
|
Katherine Parry
|
7815b81716
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-11 18:30:29 -07:00 |
|
Katherine Parry
|
b728e5054d
|
variable interations implemented in radix-4 divider
|
2022-07-11 18:30:21 -07:00 |
|
DTowersM
|
191c7a2ee3
|
added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
|
2022-07-11 21:13:09 +00:00 |
|
David Harris
|
2bc8ff555b
|
added comment about checking SRAM size
|
2022-07-10 12:48:51 +00:00 |
|
David Harris
|
9cb675b2e4
|
added comment about RAMs in cacheway
|
2022-07-10 12:47:34 +00:00 |
|
Katherine Parry
|
ca4fe08fd9
|
renamed FLoad2 to FStore2
|
2022-07-09 00:26:45 +00:00 |
|
Katherine Parry
|
cd53ae67d9
|
moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
|
cturek
|
2dc074ea93
|
F Selection
|
2022-07-08 21:53:52 +00:00 |
|
Katherine Parry
|
3476579e02
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-08 12:30:50 -07:00 |
|
Katherine Parry
|
9ef45f36fd
|
renamed signals in cvt and prostproc
|
2022-07-08 12:30:43 -07:00 |
|
James Stine
|
c5dfefe669
|
Update SRAM to /proj/wally
|
2022-07-08 08:09:55 -05:00 |
|
David Harris
|
d10ad0e883
|
Removed testbench code that ignores mismatch on zero signatures
|
2022-07-08 09:17:31 +00:00 |
|
David Harris
|
c72e4d43d2
|
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-08 09:09:07 +00:00 |
|
David Harris
|
381f3298d8
|
Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
|
2022-07-08 09:09:02 +00:00 |
|
David Harris
|
1ce0975366
|
Adjusting byte writes to RAM
|
2022-07-08 08:45:21 +00:00 |
|
David Harris
|
3f9e662201
|
Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables
|
2022-07-08 08:44:37 +00:00 |
|
David Harris
|
9b6d9666c5
|
Removed unused swbytemask from CLINT
|
2022-07-08 08:43:24 +00:00 |
|
Katherine Parry
|
905b7ffc84
|
moved unsused division code again
|
2022-07-07 16:41:26 -07:00 |
|
cturek
|
b7e590ebb0
|
Sqrt exponents
|
2022-07-07 23:34:56 +00:00 |
|
Katherine Parry
|
5751d86f69
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-07 16:29:44 -07:00 |
|
Katherine Parry
|
2bbde827e6
|
Revert "moved old divsqrt to unusedsrc"
This reverts commit c9f5ae12ea.
|
2022-07-07 16:29:17 -07:00 |
|
DTowersM
|
5a68ff9afb
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
|
2022-07-07 23:11:35 +00:00 |
|
DTowersM
|
d55833e4f3
|
new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory
|
2022-07-07 23:11:02 +00:00 |
|
Katherine Parry
|
c9f5ae12ea
|
moved old divsqrt to unusedsrc
|
2022-07-07 16:09:56 -07:00 |
|
Katherine Parry
|
41c16be012
|
srt divider merged into fpu
|
2022-07-07 16:01:33 -07:00 |
|
cturek
|
b41a6f069b
|
Seventeen Square Root Tests
|
2022-07-07 22:48:46 +00:00 |
|
David Harris
|
96a75d7749
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-07 22:00:59 +00:00 |
|
Katherine Parry
|
08769e35ae
|
modified wally shared
|
2022-07-07 21:59:43 +00:00 |
|
David Harris
|
2f342c430e
|
fixing port errors
|
2022-07-07 21:57:10 +00:00 |
|
Katherine Parry
|
0b40f38f02
|
added load and store test
|
2022-07-07 21:48:51 +00:00 |
|
cturek
|
89e17b6f3c
|
Preprocessing for square root
|
2022-07-07 21:23:30 +00:00 |
|
David Harris
|
88e3233935
|
Preliminary SRAM integration
|
2022-07-07 19:56:20 +00:00 |
|
David Harris
|
b7462ed6ed
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-07 15:51:33 +00:00 |
|
slmnemo
|
c5fd98ba99
|
sim-buildroot-batch now runs wally-pipelined-batch
with option buildroot buildroot-no-trace to boot linux from step 0
|
2022-07-06 18:06:43 -07:00 |
|
David Harris
|
6a030fc2a3
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-06 23:44:47 +00:00 |
|
DTowersM
|
47a990d9f1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
|
2022-07-06 23:44:27 +00:00 |
|
DTowersM
|
1e8ccf3449
|
added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu
|
2022-07-06 23:43:57 +00:00 |
|
David Harris
|
08ae2db080
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-06 23:43:05 +00:00 |
|
Ross Thompson
|
bd46cf76a9
|
Fixed an issue with direct map cache's nextway logic.
Also found a small error in the replacement policy.
|
2022-07-06 18:34:30 -05:00 |
|
Madeleine Masser-Frye
|
cb33d2289b
|
fixed width mismatch for rv64 ieuadrM and readdatawordM
|
2022-07-06 22:39:35 +00:00 |
|
David Harris
|
9ef38145d7
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-06 13:26:26 +00:00 |
|
David Harris
|
a599084b88
|
PLIC and UART passing tests on APB
|
2022-07-06 13:26:14 +00:00 |
|
Madeleine Masser-Frye
|
846f12aa2e
|
new priority onehot module for better area/time
|
2022-07-06 00:08:59 +00:00 |
|
Madeleine Masser-Frye
|
01e6d69a67
|
took first match out of pmpadrdec
|
2022-07-06 00:02:01 +00:00 |
|
Madeleine Masser-Frye
|
50e9b6ac53
|
fixed concatenation syntax
|
2022-07-05 22:36:54 +00:00 |
|
cturek
|
e7ac99a683
|
Radix 2 Integer division working (without signs or remainder)
|
2022-07-05 21:34:49 +00:00 |
|
David Harris
|
d73645944f
|
APB CLINT passing regression
|
2022-07-05 15:51:35 +00:00 |
|
David Harris
|
d033659beb
|
Modified uncore to use AHB bridge to GPIO
|
2022-07-05 05:02:21 +00:00 |
|
David Harris
|
e7fe7ad0c8
|
AHB bridge for gpio
|
2022-07-05 05:01:59 +00:00 |
|
David Harris
|
4723ff559c
|
Added reference to Schmookler01 for LOA
|
2022-07-05 05:01:12 +00:00 |
|
David Harris
|
aa3dc8bfe1
|
Added comments to PLIC about likely bug
|
2022-07-05 05:00:29 +00:00 |
|
David Harris
|
4c48d71e4b
|
removed delay in ahblite
|
2022-07-05 04:59:28 +00:00 |
|
David Harris
|
dab87811e9
|
Removed sig4 spurious message from testbench
|
2022-07-05 03:27:14 +00:00 |
|
David Harris
|
2b3038edf8
|
Added check to halt testbench on failing to find file
|
2022-07-05 02:28:59 +00:00 |
|
Katherine Parry
|
010a05f583
|
added missing files
|
2022-07-03 21:40:47 -07:00 |
|
Katherine Parry
|
1b4584e825
|
Renaming signals to match chapter
|
2022-07-03 12:26:22 -07:00 |
|
David Harris
|
bde1c5eb1b
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-02 19:37:14 +00:00 |
|
David Harris
|
52dbc9f8be
|
FMA ZAligned name
|
2022-07-02 19:35:13 +00:00 |
|
Katherine Parry
|
575b73fa8c
|
some prostprocessing cleanup
|
2022-07-01 14:55:46 -07:00 |
|
slmnemo
|
67fd3be9d4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-29 13:40:15 -07:00 |
|
slmnemo
|
11956d0661
|
./regression-wally -buildroot or ./regression-wally -all now builds Linux from instruction 0 instead of trying to reach instruction 246000000
|
2022-06-29 13:40:11 -07:00 |
|
Daniel Torres
|
a384a6465b
|
reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished
|
2022-06-29 12:32:30 -07:00 |
|
Daniel Torres
|
50b9b4557c
|
added changes to testbench, tests and riscof for additional riscof compatability
|
2022-06-29 12:23:40 -07:00 |
|
Katherine Parry
|
6baded9121
|
added rv32 double precision stores - untested
|
2022-06-28 21:33:31 +00:00 |
|
Katherine Parry
|
478a2e2a4b
|
removed an adder out of early termination
|
2022-06-28 18:01:11 +00:00 |
|
slmnemo
|
448c9fdbb9
|
Add CLINT tests from book
|
2022-06-27 20:09:58 -07:00 |
|
Katherine Parry
|
a3e46348c7
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-28 00:16:36 +00:00 |
|
Katherine Parry
|
f2d05911ca
|
very basic early termination passes testfloat 64-bit tests
|
2022-06-28 00:16:22 +00:00 |
|
cturek
|
3a40c68549
|
Updated radix 2 divider to work with integers and floats in new structure. Integers still might not work.
|
2022-06-27 23:55:21 +00:00 |
|
cturek
|
54938c7abf
|
Added int tests
|
2022-06-27 21:44:06 +00:00 |
|
Katherine Parry
|
f25bb4a384
|
radix-4 early termination working for special cases - not working completely
|
2022-06-27 20:43:55 +00:00 |
|
Katherine Parry
|
2d5d1f4e8f
|
radix-4 divider passing all double precision testfloat tests
|
2022-06-27 17:04:51 +00:00 |
|
Katherine Parry
|
06f7f9b147
|
fixed commented out error and removed killprod from result selection
|
2022-06-25 01:42:23 +00:00 |
|
Katherine Parry
|
d16ae7c305
|
passing regression again
|
2022-06-25 00:31:32 +00:00 |
|
Katherine Parry
|
913a381442
|
commented out error - also some divider bugs fixed
|
2022-06-25 00:04:53 +00:00 |
|
Katherine Parry
|
c1b4e7fd2c
|
modified result select to account for x/inf
|
2022-06-24 21:23:15 +00:00 |
|
Katherine Parry
|
a65c0eb679
|
radix 4 division denormal result handeling
|
2022-06-24 21:02:50 +00:00 |
|
Katherine Parry
|
d058ec6329
|
added denormal input handeling - radix 4
|
2022-06-24 19:41:40 +00:00 |
|
Katherine Parry
|
45e918b02f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-24 01:09:53 +00:00 |
|
Katherine Parry
|
fc75fc633f
|
division by zero added
|
2022-06-24 01:09:44 +00:00 |
|
slmnemo
|
51426ab71a
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-23 16:51:51 -07:00 |
|
slmnemo
|
7c019ea074
|
Removed references to initialization files
|
2022-06-23 16:50:27 -07:00 |
|
Katherine Parry
|
86cdbd90e6
|
forgot a file
|
2022-06-23 23:01:30 +00:00 |
|
Katherine Parry
|
97ded2cdd9
|
div debug - accounted for 1 bit normalization in exponent calculation
|
2022-06-23 22:59:43 +00:00 |
|
Katherine Parry
|
d17596353b
|
lint warning fix
|
2022-06-23 22:37:44 +00:00 |
|
Katherine Parry
|
b54d84195f
|
added radix-4 0/d handling
|
2022-06-23 22:36:19 +00:00 |
|
slmnemo
|
53b2487ead
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-23 14:39:59 -07:00 |
|
slmnemo
|
ded2631567
|
Removed big64.txt reference, fixing a warning
|
2022-06-23 14:39:53 -07:00 |
|
Katherine Parry
|
5133b08161
|
generate qsel4 in verilog
|
2022-06-23 21:38:04 +00:00 |
|
slmnemo
|
a77fb485db
|
Added wally32periph to regression
|
2022-06-23 14:37:18 -07:00 |
|
David Harris
|
2c4b86c703
|
Fixed typo in clint
|
2022-06-23 21:27:46 +00:00 |
|
David Harris
|
ceddc99ac9
|
Reset mtimecmp in clint
|
2022-06-23 21:20:55 +00:00 |
|
James Stine
|
79bf543ba9
|
Update
|
2022-06-23 11:59:05 -05:00 |
|
James Stine
|
001e8e077d
|
Add sqrt qlsc table generator
|
2022-06-23 11:46:44 -05:00 |
|
Katherine Parry
|
49067792dc
|
fixt lint error
|
2022-06-23 16:11:50 +00:00 |
|