slmnemo 99dcff80c9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2022-07-21 20:35:52 -07:00
..
config	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00
src	Fixed UART bug related to parity and MSR/LSR	2022-07-21 20:35:46 -07:00
srt	Changed testbench to operate on two inputs and one output, changed all test generators, changed srt module to return only one output and take in Mod as a signal to compute integer remainder	2022-07-22 01:27:08 +00:00
testbench	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-21 12:50:04 -07:00